📄 psocconfigtbl.lst
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562 ;----------------------------------------------------
563 ; Sleep, CPU Stop & Software Reset
564 ;----------------------------------------------------
565 macro M8C_Sleep
566 or reg[CPU_SCR0], CPU_SCR0_SLEEP_MASK
567 ; The next instruction to be executed depends on the state of the
568 ; various interrupt enable bits. If some interrupts are enabled
569 ; and the global interrupts are disabled, the next instruction will
570 ; be the one that follows the invocation of this macro. If global
571 ; interrupts are also enabled then the next instruction will be
572 ; from the interrupt vector table. If no interrupts are enabled
573 ; then the CPU sleeps forever.
574 1C5C endm
575
576 macro M8C_Stop
577 ; In general, you probably don't want to do this, but here's how:
578 or reg[CPU_SCR0], CPU_SCR0_STOP_MASK
579 ; Next instruction to be executed is located in the interrupt
580 ; vector table entry for Power-On Reset.
581 1C5C endm
582
583 macro M8C_Reset
584 ; Restore CPU to the power-on reset state.
585 mov A, 0
586 SSC
587 ; Next non-supervisor instruction will be at interrupt vector 0.
588 1C5C endm
589
590 ;----------------------------------------------------
591 ; ImageCraft Code Compressor Actions
592 ;----------------------------------------------------
593 ; Suspend Code Compressor
594 ; Must not span a RET or RETI instruction
595 ; without resuming code compression
596 macro Suspend_CodeCompressor
597 or F, 0
598 1C5C endm
599
600 ; Resume Code Compression
601 macro Resume_CodeCompressor
602 add SP, 0
603 1C5C endm
1 ; Generated by PSoC Designer ???
2 ;
3 include "m8c.inc"
4 ; Personalization tables
5 export LoadConfigTBL_mf_temp_Bank1
6 export LoadConfigTBL_mf_temp_Bank0
7 export LoadConfigTBL_mf_temp_Ordered
8 AREA lit(rom, rel)
9 072D LoadConfigTBL_mf_temp_Ordered:
10 ; Ordered Global Register values
11 072D 71 10 M8C_SetBank1
12 072F 62 00 00 mov reg[00h], 00h ; Port_0_DriveMode_0 register (PRT0DM0)
13 0732 62 01 FF mov reg[01h], ffh ; Port_0_DriveMode_1 register (PRT0DM1)
14 0735 70 EF M8C_SetBank0
15 0737 62 03 FF mov reg[03h], ffh ; Port_0_DriveMode_2 register (PRT0DM2)
16 073A 62 02 00 mov reg[02h], 00h ; Port_0_GlobalSelect register (PRT0GS)
17 073D 71 10 M8C_SetBank1
18 073F 62 02 00 mov reg[02h], 00h ; Port_0_IntCtrl_0 register (PRT0IC0)
19 0742 62 03 00 mov reg[03h], 00h ; Port_0_IntCtrl_1 register (PRT0IC1)
20 0745 70 EF M8C_SetBank0
21 0747 62 01 00 mov reg[01h], 00h ; Port_0_IntEn register (PRT0IE)
22 074A 71 10 M8C_SetBank1
23 074C 62 04 E0 mov reg[04h], e0h ; Port_1_DriveMode_0 register (PRT1DM0)
24 074F 62 05 BF mov reg[05h], bfh ; Port_1_DriveMode_1 register (PRT1DM1)
25 0752 70 EF M8C_SetBank0
26 0754 62 07 BF mov reg[07h], bfh ; Port_1_DriveMode_2 register (PRT1DM2)
27 0757 62 06 40 mov reg[06h], 40h ; Port_1_GlobalSelect register (PRT1GS)
28 075A 71 10 M8C_SetBank1
29 075C 62 06 00 mov reg[06h], 00h ; Port_1_IntCtrl_0 register (PRT1IC0)
30 075F 62 07 00 mov reg[07h], 00h ; Port_1_IntCtrl_1 register (PRT1IC1)
31 0762 70 EF M8C_SetBank0
32 0764 62 05 00 mov reg[05h], 00h ; Port_1_IntEn register (PRT1IE)
33 0767 71 10 M8C_SetBank1
34 0769 62 08 00 mov reg[08h], 00h ; Port_2_DriveMode_0 register (PRT2DM0)
35 076C 62 09 FF mov reg[09h], ffh ; Port_2_DriveMode_1 register (PRT2DM1)
36 076F 70 EF M8C_SetBank0
37 0771 62 0B FF mov reg[0bh], ffh ; Port_2_DriveMode_2 register (PRT2DM2)
38 0774 62 0A 00 mov reg[0ah], 00h ; Port_2_GlobalSelect register (PRT2GS)
39 0777 71 10 M8C_SetBank1
40 0779 62 0A 00 mov reg[0ah], 00h ; Port_2_IntCtrl_0 register (PRT2IC0)
41 077C 62 0B 00 mov reg[0bh], 00h ; Port_2_IntCtrl_1 register (PRT2IC1)
42 077F 70 EF M8C_SetBank0
43 0781 62 09 00 mov reg[09h], 00h ; Port_2_IntEn register (PRT2IE)
44 0784 71 10 M8C_SetBank1
45 0786 62 0C 00 mov reg[0ch], 00h ; Port_3_DriveMode_0 register (PRT3DM0)
46 0789 62 0D 0F mov reg[0dh], 0fh ; Port_3_DriveMode_1 register (PRT3DM1)
47 078C 70 EF M8C_SetBank0
48 078E 62 0F 0F mov reg[0fh], 0fh ; Port_3_DriveMode_2 register (PRT3DM2)
49 0791 62 0E 00 mov reg[0eh], 00h ; Port_3_GlobalSelect register (PRT3GS)
50 0794 71 10 M8C_SetBank1
51 0796 62 0E 00 mov reg[0eh], 00h ; Port_3_IntCtrl_0 register (PRT3IC0)
52 0799 62 0F 00 mov reg[0fh], 00h ; Port_3_IntCtrl_1 register (PRT3IC1)
53 079C 70 EF M8C_SetBank0
54 079E 62 0D 00 mov reg[0dh], 00h ; Port_3_IntEn register (PRT3IE)
55 07A1 7F ret
56 07A2 LoadConfigTBL_mf_temp_Bank0:
57 ; Global Register values
58 07A2 60 08 db 60h, 08h ; AnalogColumnInputSelect register (AMX_IN)
59 07A4 64 00 db 64h, 00h ; AnalogComparatorControl0 register (CMP_CR0)
60 07A6 66 00 db 66h, 00h ; AnalogComparatorControl1 register (CMP_CR1)
61 07A8 61 00 db 61h, 00h ; AnalogMuxBusConfig register (AMUXCFG)
62 07AA E6 20 db e6h, 20h ; DecimatorControl_0 register (DEC_CR0)
63 07AC E7 00 db e7h, 00h ; DecimatorControl_1 register (DEC_CR1)
64 07AE D6 04 db d6h, 04h ; I2CConfig register (I2CCFG)
65 07B0 62 00 db 62h, 00h ; PWM_Control register (PWM_CR)
66 07B2 B0 00 db b0h, 00h ; Row_0_InputMux register (RDI0RI)
67 07B4 B1 00 db b1h, 00h ; Row_0_InputSync register (RDI0SYN)
68 07B6 B2 00 db b2h, 00h ; Row_0_LogicInputAMux register (RDI0IS)
69 07B8 B3 33 db b3h, 33h ; Row_0_LogicSelect_0 register (RDI0LT0)
70 07BA B4 33 db b4h, 33h ; Row_0_LogicSelect_1 register (RDI0LT1)
71 07BC B5 00 db b5h, 00h ; Row_0_OutputDrive_0 register (RDI0SRO0)
72 07BE B6 08 db b6h, 08h ; Row_0_OutputDrive_1 register (RDI0SRO1)
73 ; Instance name ADC10, User Module ADC10
74 ; Instance name ADC10, Block Name ADC(ACE01)
75 07C0 76 69 db 76h, 69h ;ADC10_ACE_CR1(ACE01CR1)
76 07C2 77 00 db 77h, 00h ;ADC10_ACE_CR2(ACE01CR2)
77 ; Instance name ADC10, Block Name CNT(DBB00)
78 07C4 23 00 db 23h, 00h ;ADC10_CNT_CR0(DBB00CR0)
79 07C6 21 00 db 21h, 00h ;ADC10_CNT_DR1(DBB00DR1)
80 07C8 22 00 db 22h, 00h ;ADC10_CNT_DR2(DBB00DR2)
81 ; Instance name ADC10, Block Name RAMP(ASE11)
82 07CA 69 64 db 69h, 64h ;ADC10_ADC_CR(ADC1_CR)
83 07CC 84 00 db 84h, 00h ;ADC10_ASE_CR0(ASE11CR0)
84 ; Instance name AMUX8, User Module AMUX8
85 ; Instance name EzI2Cs, User Module EzI2Cs
86 ; Instance name PWM_01, User Module PWM8
87 ; Instance name PWM_01, Block Name PWM8(DBB01)
88 07CE 27 00 db 27h, 00h ;PWM_01_CONTROL_REG(DBB01CR0)
89 07D0 25 F9 db 25h, f9h ;PWM_01_PERIOD_REG(DBB01DR1)
90 07D2 26 64 db 26h, 64h ;PWM_01_COMPARE_REG(DBB01DR2)
91 ; Instance name SHADOWREGS_0, User Module SHADOWREGS
92 ; Instance name SHADOWREGS_1, User Module SHADOWREGS
93 ; Instance name SHADOWREGS_2, User Module SHADOWREGS
94 ; Instance name SHADOWREGS_3, User Module SHADOWREGS
95 ; Instance name SystemTimer, User Module SleepTimer
96 07D4 FF db ffh
97 07D5 LoadConfigTBL_mf_temp_Bank1:
98 ; Global Register values
99 07D5 61 00 db 61h, 00h ; AnalogClockSelect1 register (CLK_CR1)
100 07D7 60 00 db 60h, 00h ; AnalogColumnClockSelect register (CLK_CR0)
101 07D9 62 00 db 62h, 00h ; AnalogIOControl_0 register (ABF_CR0)
102 07DB 67 33 db 67h, 33h ; AnalogLUTControl0 register (ALT_CR0)
103 07DD 64 00 db 64h, 00h ; ComparatorGlobalOutEn register (CMP_GO_EN)
104 07DF FD 00 db fdh, 00h ; DAC_Control register (DAC_CR)
105 07E1 D1 00 db d1h, 00h ; GlobalDigitalInterconnect_Drive_Even_Input register (GDI_E_IN)
106 07E3 D3 00 db d3h, 00h ; GlobalDigitalInterconnect_Drive_Even_Output register (GDI_E_OU)
107 07E5 D0 00 db d0h, 00h ; GlobalDigitalInterconnect_Drive_Odd_Input register (GDI_O_IN)
108 07E7 D2 00 db d2h, 00h ; GlobalDigitalInterconnect_Drive_Odd_Output register (GDI_O_OU)
109 07E9 E1 B7 db e1h, b7h ; OscillatorControl_1 register (OSC_CR1)
110 07EB E2 00 db e2h, 00h ; OscillatorControl_2 register (OSC_CR2)
111 07ED DF 7F db dfh, 7fh ; OscillatorControl_3 register (OSC_CR3)
112 07EF DE 01 db deh, 01h ; OscillatorControl_4 register (OSC_CR4)
113 07F1 DD 00 db ddh, 00h ; OscillatorGlobalBusEnableControl register (OSC_GO_EN)
114 07F3 D8 00 db d8h, 00h ; Port_0_MUXBusCtrl register (MUX_CR0)
115 07F5 D9 00 db d9h, 00h ; Port_1_MUXBusCtrl register (MUX_CR1)
116 07F7 DA 00 db dah, 00h ; Port_2_MUXBusCtrl register (MUX_CR2)
117 07F9 DB 00 db dbh, 00h ; Port_3_MUXBusCtrl register (MUX_CR3)
118 ; Instance name ADC10, User Module ADC10
119 ; Instance name ADC10, Block Name ADC(ACE01)
120 ; Instance name ADC10, Block Name CNT(DBB00)
121 07FB 20 21 db 20h, 21h ;ADC10_CNT_FN(DBB00FN)
122 07FD 21 55 db 21h, 55h ;ADC10_CNT_IN(DBB00IN)
123 07FF 22 40 db 22h, 40h ;ADC10_CNT_OUT(DBB00OU)
124 ; Instance name ADC10, Block Name RAMP(ASE11)
125 0801 E6 00 db e6h, 00h ;ADC10_ADC_TR(ADC1_TR)
126 0803 66 00 db 66h, 00h ;ADC10_(AMD_CR1)
127 ; Instance name AMUX8, User Module AMUX8
128 ; Instance name EzI2Cs, User Module EzI2Cs
129 ; Instance name PWM_01, User Module PWM8
130 ; Instance name PWM_01, Block Name PWM8(DBB01)
131 0805 24 31 db 24h, 31h ;PWM_01_FUNC_REG(DBB01FN)
132 0807 25 16 db 25h, 16h ;PWM_01_INPUT_REG(DBB01IN)
133 0809 26 46 db 26h, 46h ;PWM_01_OUTPUT_REG(DBB01OU)
134 ; Instance name SHADOWREGS_0, User Module SHADOWREGS
135 ; Instance name SHADOWREGS_1, User Module SHADOWREGS
136 ; Instance name SHADOWREGS_2, User Module SHADOWREGS
137 ; Instance name SHADOWREGS_3, User Module SHADOWREGS
138 ; Instance name SystemTimer, User Module SleepTimer
139 080B FF db ffh
HI-TECH Software Macro Assembler (PSoC MCU) V9.61PL1
Symbol Table Fri Oct 03 08:10:15 2008
LoadConfigTBL_mf_temp_Bank0 07A2 LoadConfigTBL_mf_temp_Bank1 07D5 LoadConfigTBL_mf_temp_Ordered 072D
FLAG_XIO_MASK 0010
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