at91_cstartup.s79

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;-----------------------------------------------------------------------------
; This file contains the startup code used by the ICCARM C compiler.
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; All code in the modules (except ?RESET) will be placed in the ICODE segment.
;
; $Revision: 1.9 $
;
;-----------------------------------------------------------------------------

#include "config.h"

;
; Naming covention of labels in this file:
;
;  ?xxx	  - External labels only accessed from assembler.
;  __xxx  - External labels accessed from or defined in C.
;  xxx	  - Labels local to one module (note: this file contains 
;           several modules).
;  main	  - The starting point of the user program.
;

;---------------------------------------------------------------
; Macros and definitions for the whole file
;---------------------------------------------------------------

; Mode, correspords to bits 0-5 in CPSR
MODE_BITS	DEFINE	0x1F		; Bit mask for mode bits in CPSR
USR_MODE	DEFINE	0x10		; User mode
FIQ_MODE	DEFINE	0x11		; Fast Interrupt Request mode
IRQ_MODE	DEFINE	0x12		; Interrupt Request mode
SVC_MODE	DEFINE	0x13		; Supervisor mode
ABT_MODE	DEFINE	0x17		; Abort mode
UND_MODE	DEFINE	0x1B		; Undefined Instruction mode
SYS_MODE	DEFINE	0x1F		; System mode
	

;---------------------------------------------------------------
; ?RESET
; Reset Vector.
; Normally, segment INTVEC is linked at address 0.
; For debugging purposes, INTVEC may be placed at other
; addresses.
; A debugger that honors the entry point will start the
; program in a normal way even if INTVEC is not at address 0.
;---------------------------------------------------------------

		MODULE	?RESET
		COMMON	INTVEC:CODE:NOROOT(2)
		PUBLIC  __program_start
		EXTERN	?boot
		EXTERN	undef_handler, swi_handler, prefetch_handler
		EXTERN	data_handler, irq_handler, fiq_handler
		CODE32	; Always ARM mode after reset	
		org	0x00
__program_start
#if FLASHCODE
		b	?boot ; Relative branch allows remap
#else
		ldr	pc,=?boot ; Absolute jump can reach above 0x2000000
#endif
		org	0x04
;		ldr	pc,=undef_handler
		org	0x08
;		ldr	pc,=swi_handler
		org	0x0c
;		ldr	pc,=prefetch_handler
		org	0x10
;		ldr	pc,=data_handler
		org	0x18
;		ldr	pc,=irq_handler
		org	0x1c
;		ldr	pc,=fiq_handler

		; Constant table entries (for ldr pc) will be placed at 0x20
		org	0x20
		LTORG
;		ENDMOD	__program_start
                ENDMOD


;---------------------------------------------------------------
; ?BOOT
;---------------------------------------------------------------
		MODULE	?BOOT
		RSEG	ICODE:CODE:NOROOT(2)
		EXTERN	?cstartup
		CODE32
		PUBLIC ?boot
?boot:
#if AT91_REMAP
                ; The memory controller is initialized immediately before the remap
                ldr     r10, =EBI_init_table ; EBI register initialization table
                ; If pc > 0x100000
                movs    r0, pc, LSR #20
                ; Mask the 12 highest bits of the address
                moveq   r10, r10, LSL #12
                moveq   r10, r10, LSR #12

                ; Load the address where to jump
                ldr     r12, =after_remap ; get the real jump address ( after remap )

                ; Copy chip select register image to memory controller and command remap
                ldmia   r10!, {r0-r9,r11}       ; load the complete image and the EBI base
                stmia   r11!, {r0-r9}           ; store the complete image with the remap command

                ; jump to ROM at its new address
                ; this instruction was loaded into the pipeline before the remap was done
                mov         pc, r12             ; jump and break the pipeline

                ; Put constant table here.
                LTORG

                ; EBI initialization table
                ; 32,768 MHz master clock assumed for timing
EBI_init_table:
                dc32        0x0100252d  ; Flash at 0x01000000, 16MB, 2 hold, 16 bits, 4 WS
                dc32        0x02002121  ; RAM   at 0x02000000,  1MB, 0 hold, 16 bits, 1 WS
                dc32        0x20000000  ; unused
                dc32        0x30000000  ; unused
                dc32        0x40000000  ; unused
                dc32        0x50000000  ; unused
                dc32        0x60000000  ; unused
                dc32        0x70000000  ; unused
                dc32        0x00000001  ; REMAP command
                dc32        0x00000006  ; standard read
                dc32        __EBI_CSR0  ; EBI Base address

after_remap:
#endif
                ; Execute C startup code.
                b           ?cstartup
		ENDMOD ?boot		; Entry point = ?boot


;---------------------------------------------------------------
; ?CSTARTUP
;---------------------------------------------------------------
		MODULE	?CSTARTUP

		RSEG	IRQ_STACK:DATA(2)
		RSEG	SVC_STACK:DATA:NOROOT(2)
		RSEG	CSTACK:DATA(2)
		RSEG	ICODE:CODE:NOROOT(2)
		PUBLIC	?cstartup
		EXTERN	?main

; Execution starts here.
; After a reset, the mode is ARM, Supervisor, interrupts disabled.


		CODE32
?cstartup

; Add initialization nedded before setup of stackpointers here


; Initialize the stack pointers.
; The pattern below can be used for any of the exception stacks:
; FIQ, IRQ, SVC, ABT, UND, SYS.
; The USR mode uses the same stack as SYS. 
; The stack segments must be defined in the linker command file,
; and be declared above.
                mrs     r0,cpsr                             ; Original PSR value
                bic     r0,r0,#MODE_BITS                    ; Clear the mode bits
                orr     r0,r0,#IRQ_MODE                     ; Set IRQ mode bits
                msr     cpsr_c,r0                           ; Change the mode
                ldr     sp,=SFE(IRQ_STACK) & 0xFFFFFFF8     ; End of IRQ_STACK
                
                bic     r0,r0,#MODE_BITS                    ; Clear the mode bits
                orr     r0,r0,#SYS_MODE                     ; Set System mode bits
                msr     cpsr_c,r0                           ; Change the mode
                ldr     sp,=SFE(CSTACK) & 0xFFFFFFF8        ; End of CSTACK

#ifdef __ARMVFP__
; Enable the VFP coprocessor.
                mov     r0, #0x40000000                 ; Set EN bit in VFP
                fmxr    fpexc, r0                       ; FPEXC, clear others.

; Disable underflow exceptions by setting flush to zero mode.
; For full IEEE 754 underflow compliance this code should be removed
; and the appropriate exception handler installed.
                mov     r0, #0x01000000		        ; Set FZ bit in VFP
                fmxr    fpscr, r0                       ; FPSCR, clear others.
#endif
        
; Add more initialization here


; Continue to ?main for more IAR specific system startup

                ldr     r0,=?main        
                bx      r0        
            
                LTORG
                            
                ENDMOD
            
            
                END