davincihd_dsp.gel.txt

来自「基于 TMS320DM6467 DaVinci&#8482 处理器的开发板设计」· 文本 代码 · 共 352 行 · 第 1/2 页

    GEL_MapAddStr( 0x40440000, 0, 0x00040000, "R|W|AS4", 0 );   // HD-VICP0 R-Only Port
    GEL_MapAddStr( 0x40480000, 0, 0x00040000, "R|W|AS4", 0 );   // HD-VICP0 W-Only Port

    /* HD-VICP1 */
    GEL_MapAddStr( 0x00600000, 0, 0x00100000, "R|W|AS4", 0 );   // HD-VICP1
    GEL_MapAddStr( 0x11600000, 0, 0x00100000, "R|W|AS4", 0 );   // HD-VICP1
    GEL_MapAddStr( 0x40600000, 0, 0x00040000, "R|W|AS4", 0 );   // HD-VICP1 R/W Port
    GEL_MapAddStr( 0x40640000, 0, 0x00040000, "R|W|AS4", 0 );   // HD-VICP1 R-Only Port
    GEL_MapAddStr( 0x40680000, 0, 0x00040000, "R|W|AS4", 0 );   // HD-VICP1 W-Only Port

    /* DSP RAM */
    GEL_MapAddStr( 0x00818000, 0, 0x00020000, "R|W|AS4", 0 );   // DSP L2 RAM/Cache
    GEL_MapAddStr( 0x00e00000, 0, 0x00008000, "R|W|AS4", 0 );   // DSP L1P Cache/RAM
    GEL_MapAddStr( 0x00f00000, 0, 0x00008000, "R|W|AS4", 0 );   // DSP L1D Cache/RAM
    GEL_MapAddStr( 0x11818000, 0, 0x00020000, "R|W|AS4", 0 );   // DSP L2 RAM/Cache
    GEL_MapAddStr( 0x11e00000, 0, 0x00008000, "R|W|AS4", 0 );   // DSP L1P Cache/RAM
    GEL_MapAddStr( 0x11f00000, 0, 0x00008000, "R|W|AS4", 0 );   // DSP L1D Cache/RAM

    /* DDR2 */
    GEL_MapAddStr( 0x20000000, 0, 0x000000f4, "R|W|AS4", 0 );   // DDR2 Control
    GEL_MapAddStr( 0x80000000, 0, 0x40000000, "R|W|AS4", 0 );   // DDR2 SDRAM

    /* EMIFA */
    GEL_MapAddStr( 0x20008000, 0, 0x00000080, "R|W|AS4", 0 );   // EMIFA Control
    GEL_MapAddStr( 0x42000000, 0, 0x02000000, "R|W|AS4", 0 );   // AEMIF CS2
    GEL_MapAddStr( 0x44000000, 0, 0x02000000, "R|W|AS4", 0 );   // AEMIF CS3
    GEL_MapAddStr( 0x46000000, 0, 0x02000000, "R|W|AS4", 0 );   // AEMIF CS4
    GEL_MapAddStr( 0x48000000, 0, 0x02000000, "R|W|AS4", 0 );   // AEMIF CS5

    /* VLYNQ */
    GEL_MapAddStr( 0x20010000, 0, 0x00000048, "R|W|AS4", 0 );   // VLYNQ Control
  //GEL_MapAddStr( 0x20010080, 0, 0x00000068, "R|W|AS4", 0 );   // VLYNQ Control Remote
    GEL_MapAddStr( 0x4c000000, 0, 0x04000000, "R|W|AS4", 0 );   // VLYNQ Remote Devices

    /* PCI */
    GEL_MapAddStr( 0x30000000, 0, 0x10000000, "R|W|AS4", 0 );   // PCI Address Space

}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Clear_Memory_Map( )                                                     *
 *      Clear the Memory Map                                                *
 *                                                                          *
 * ------------------------------------------------------------------------ */
hotmenu
Clear_Memory_Map( )
{
    GEL_MapOff( );
    GEL_MapReset( );
}

menuitem "DaVinci HD Functions";

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Setup_Cache( )                                                          *
 *      Invalidate old cache and setup cache for operation                  *
 *                                                                          *
 * ------------------------------------------------------------------------ */
hotmenu
Setup_Cache( )
{
    int l1p, l1d, l2;

    GEL_TextOut( "Setup Cache " );
    #define CACHE_L2CFG         *( unsigned int* )( 0x01840000 )
    #define CACHE_L2INV         *( unsigned int* )( 0x01845008 )
    #define CACHE_L1PCFG        *( unsigned int* )( 0x01840020 )
    #define CACHE_L1PINV        *( unsigned int* )( 0x01845028 )
    #define CACHE_L1DCFG        *( unsigned int* )( 0x01840040 )
    #define CACHE_L1DINV        *( unsigned int* )( 0x01845048 )

    CACHE_L1PINV = 1;           // L1P invalidated
    CACHE_L1PCFG = 7;           // L1P on, MAX size
    CACHE_L1DINV = 1;           // L1D invalidated
    CACHE_L1DCFG = 7;           // L1D on, MAX size
    CACHE_L2INV  = 1;           // L2 invalidated
    CACHE_L2CFG  = 0;           // L2 off, use as RAM

    l1p = CACHE_L1PCFG;
    if ( l1p == 0 )
        GEL_TextOut( "(L1P = 0K) + " );
    if ( l1p == 1 )
        GEL_TextOut( "(L1P = 4K) + " );
    if ( l1p == 2 )
        GEL_TextOut( "(L1P = 8K) + " );
    if ( l1p == 3 )
        GEL_TextOut( "(L1P = 16K) + " );
    if ( l1p >= 4 )
        GEL_TextOut( "(L1P = 32K) + " );

    l1d = CACHE_L1DCFG;
    if ( l1d == 0 )
        GEL_TextOut( "(L1D = 0K) + " );
    if ( l1d == 1 )
        GEL_TextOut( "(L1D = 4K) + " );
    if ( l1d == 2 )
        GEL_TextOut( "(L1D = 8K) + " );
    if ( l1d == 3 )
        GEL_TextOut( "(L1D = 16K) + " );
    if ( l1d >= 4 )
        GEL_TextOut( "(L1D = 32K) + " );

    l2 = CACHE_L2CFG;
    if ( l2 == 0 )
        GEL_TextOut( "(L2 = ALL SRAM)... " );
    else if ( l2 == 1 )
        GEL_TextOut( "(L2 = 31/32 SRAM)... " );
    else if ( l2 == 2 )
        GEL_TextOut( "(L2 = 15/16 SRAM)... " );
    else if ( l2 == 3 )
        GEL_TextOut( "(L2 = 7/8 SRAM)... " );
    else if ( l2 == 7 )
        GEL_TextOut( "(L2 = 3/4 SRAM)... " );

    GEL_TextOut( "[Done]\n" );
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Disable_VPSS( )                                                         *
 *      Disable VPFE & VPBE                                                 *
 *                                                                          *
 * ------------------------------------------------------------------------ */
Disable_VPSS( )
{
    #define VPIF_CHCTRL0            *( unsigned int* )( 0x01c12004 )
    #define VPIF_CHCTRL1            *( unsigned int* )( 0x01c12008 )
    #define VPIF_CHCTRL2            *( unsigned int* )( 0x01c1200c )
    #define VPIF_CHCTRL3            *( unsigned int* )( 0x01c12010 )
    #define VPIF_INTEN              *( unsigned int* )( 0x01c12020 )
    #define VPIF_INTENCLR           *( unsigned int* )( 0x01c12028 )

    GEL_TextOut( "Disable VPSS\n" );
    VPIF_CHCTRL0 = 0;
    VPIF_CHCTRL1 = 0;
    VPIF_CHCTRL2 = 0;
    VPIF_CHCTRL3 = 0;

    VPIF_INTEN = 0;
    VPIF_INTENCLR = 0x0f;

    /* Clear Channels */
  //GEL_MemoryFill( 0x01c12040, 0, 104, 0 ); // Channel 0-3
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  Disable_EDMA( )                                                         *
 *      Disabe EDMA events and interrupts, clear any pending events         *
 *                                                                          *
 * ------------------------------------------------------------------------ */
Disable_EDMA( )
{
    #define EDMA_3CC_IECRH          *( int* )( 0x01C0105C )
    #define EDMA_3CC_EECRH          *( int* )( 0x01C0102C )
    #define EDMA_3CC_ICRH           *( int* )( 0x01C01074 )
    #define EDMA_3CC_ECRH           *( int* )( 0x01C0100C )

    #define EDMA_3CC_IECR           *( int* )( 0x01C01058 )
    #define EDMA_3CC_EECR           *( int* )( 0x01C01028 )
    #define EDMA_3CC_ICR            *( int* )( 0x01C01070 )
    #define EDMA_3CC_ECR            *( int* )( 0x01C01008 )

    GEL_TextOut( "Disable EDMA events\n" );
    EDMA_3CC_IECRH  = 0xFFFFFFFF;   // IERH ( disable high interrupts )
    EDMA_3CC_EECRH  = 0xFFFFFFFF;   // EERH ( disable high events )
    EDMA_3CC_ICRH   = 0xFFFFFFFF;   // ICRH ( clear high interrupts )
    EDMA_3CC_ECRH   = 0xFFFFFFFF;   // ICRH ( clear high events )

    EDMA_3CC_IECR   = 0xFFFFFFFF;   // IER  ( disable low interrupts )
    EDMA_3CC_EECR   = 0xFFFFFFFF;   // EER  ( disable low events )
    EDMA_3CC_ICR    = 0xFFFFFFFF;   // ICR  ( clear low interrupts )
    EDMA_3CC_ECR    = 0xFFFFFFFF;   // ICRH ( clear low events )
}