📄 davincihd_arm_si_729mhz.gel.txt
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}
hotmenu DDR32bitInit_297MHZ()
{
//Program PHY Control Register
*(unsigned int*) DDRCTL1 = 0x000080C7; // RL=7
//Program SDRAM Bank Config Register
*(unsigned int*) SDCFG = 0x08D38A32; // CL=5, Bank=3
//Program SDRAM Timing Control Register
*(unsigned int*) SDTIM0 = 0x4B245C12;
*(unsigned int*) SDTIM1 = 0x3B2BC742;
//Program SDRAM Bank Config Register
*(unsigned int*) SDCFG = 0x08530A32; // Clear TIMUNLOCK bit
//Program SDRAM Refresh Control Register
*(unsigned int*) SDREF = 0x0000090D; // 7.8 x 297 = 2316.6 => 2317
GEL_TextOut("DDR2 init is done for 297MHz 32-bit Interface\n");
}
hotmenu DDR32bitInit_310_5MHZ()
{
//Program PHY Control Register
*(unsigned int*) DDRCTL1 = 0x000080C7; // RL=7
//Program SDRAM Bank Config Register
*(unsigned int*) SDCFG = 0x08D38A32; // CL=5, Bank=3
//Program SDRAM Timing Control Register
*(unsigned int*) SDTIM0 = 0x4F24645A;
*(unsigned int*) SDTIM1 = 0x3B2DC742;
//Program SDRAM Bank Config Register
*(unsigned int*) SDCFG = 0x08530A32; // Clear TIMUNLOCK bit
//Program SDRAM Refresh Control Register
*(unsigned int*) SDREF = 0x00000976; // 7.8 x 310.5 = 2421.9 => 2422
GEL_TextOut("DDR2 init is done for 310.5MHz 32-bit Interface\n");
}
menuitem "DM6467 AEMIF Configuration";
hotmenu AEMIFClksTurnOn()
{
unsigned int PdNum = 0, domainOn = 0;
*(unsigned int*) MDCTL_AEMIF = *(unsigned int*) MDCTL_AEMIF | 0x3;
/* Make sure Power Domain 0 (Always On) is ON */
domainOn = (*(unsigned int*) PDSTAT) & 0x00000001;
if(domainOn == 0)
{
GEL_TextOut("ERR: Power Domain 0 is not ON\n");
}
*(unsigned int*) PTCMD = (1<<PdNum);
while(! (((*(unsigned int*)PTSTAT >> PdNum) & 0x00000001) == 0));
while(!((*(unsigned int*)MDSTAT_AEMIF & 0x0000001F) == 0x3));
GEL_TextOut("AEMIF Controller Clocks are Turned On\n");
}
hotmenu AEMIF16Init()
{
// Enable AEMIF Pinmux (PCIEN = 0 & HPIEN = 0 & ATAEN = 0)
*(unsigned int*) PINMUX0 = *(unsigned int*) PINMUX0 & 0xFFFFFFF8;
//ASYNC EMIF Configuration
//Program Asynchronous Wait Cycles Configuration Control Register
*(unsigned int*) WAITCFG = *(unsigned int*) WAITCFG | 0x0 ;
//Program Asynchronous Bank1 Configuration Control Register
*(unsigned int*) ACFG2 = 0x3FFFFFFD;
//Program Asynchronous Bank2 Configuration Control Register
*(unsigned int*) ACFG3 = 0x3FFFFFFD;
//Program Asynchronous Bank3 Configuration Control Register
*(unsigned int*) ACFG4 = 0x3FFFFFFD;
//Program Asynchronous Bank4 Configuration Control Register
*(unsigned int*) ACFG5 = 0x3FFFFFFD;
GEL_TextOut("AEMIF init is done for 16-bit Interface\n");
}
/********************************************************
* DM6467 PLL Initialization Code
**********************************************************/
#define PLL1_BASE_ADDR 0x01C40800
#define PLL2_BASE_ADDR 0x01C40C00
/*PLL1 Controller Control Register=> Gerates clocks to DSP, ARM, VBUS, CFG, ETC*/
#define PLL1_PLLCTL (PLL1_BASE_ADDR + 0x100) /*PLL Control Register*/
#define PLL1_OCSEL (PLL1_BASE_ADDR + 0x104) /*OBSCLK Select Register*/
#define PLL1_SECCTL (PLL1_BASE_ADDR + 0x108) /*PLL Secondary Control Register*/
#define PLL1_PLLM (PLL1_BASE_ADDR + 0x110) /*PLL Multiplier Control Register*/
#define PLL1_PREDIV (PLL1_BASE_ADDR + 0x114) /*PLL Pre-Divider control Register*/
#define PLL1_PLLDVI1 (PLL1_BASE_ADDR + 0x118) /*PLL Controller Div1 Register*/
#define PLL1_PLLDVI2 (PLL1_BASE_ADDR + 0x11C) /*PLL Controller Div2 Register*/
#define PLL1_PLLDVI3 (PLL1_BASE_ADDR + 0x120) /*PLL Controller Div3 Register*/
#define PLL1_OSCDIV1 (PLL1_BASE_ADDR + 0x124) /*Oscilator Divider Register*/
#define PLL1_POSTDIV (PLL1_BASE_ADDR + 0x128) /*PLL Post-Divider Register*/
#define PLL1_BPDIV (PLL1_BASE_ADDR + 0x12C) /*Bypass Divider Register*/
#define PLL1_WAKEUP (PLL1_BASE_ADDR + 0x130) /*Wakeup Register*/
#define PLL1_PLLCMD (PLL1_BASE_ADDR + 0x138) /*PLL Controller Command Register*/
#define PLL1_PLLSTAT (PLL1_BASE_ADDR + 0x13C) /*PLL Controller Status Register*/
#define PLL1_ALNCTL (PLL1_BASE_ADDR + 0x140) /*PLL Controller Clock Align Control Register*/
#define PLL1_DCHANGE (PLL1_BASE_ADDR + 0x144) /*PLLDiv Ratio Change status Register*/
#define PLL1_CKEN (PLL1_BASE_ADDR + 0x148) /*Clock Enable Control Register*/
#define PLL1_CKSTAT (PLL1_BASE_ADDR + 0x14C) /*Clock Status Register*/
#define PLL1_SYSTAT (PLL1_BASE_ADDR + 0x150) /*SYSCLK Status Register*/
#define PLL1_PLLDIV4 (PLL1_BASE_ADDR + 0x160) /*PLL Controller Div4 Register*/
#define PLL1_PLLDIV5 (PLL1_BASE_ADDR + 0x164) /*PLL Controller Div5 Register*/
#define PLL1_PLLDIV6 (PLL1_BASE_ADDR + 0x168) /*PLL Controller Div6 Register*/
#define PLL1_PLLDIV7 (PLL1_BASE_ADDR + 0x16C) /*PLL Controller Div7 Register*/
#define PLL1_PLLDIV8 (PLL1_BASE_ADDR + 0x170) /*PLL Controller Div8 Register*/
#define PLL1_PLLDIV9 (PLL1_BASE_ADDR + 0x174) /*PLL Controller Div9 Register*/
/*PLL2 Controller Control Register=> Generages clocks to DDR2 PHY */
#define PLL2_PLLCTL (PLL2_BASE_ADDR + 0x100) /*PLL Control Register*/
#define PLL2_OCSEL (PLL2_BASE_ADDR + 0x104) /*OBSCLK Select Register*/
#define PLL2_SECCTL (PLL2_BASE_ADDR + 0x108) /*PLL Secondary Control Register*/
#define PLL2_PLLM (PLL2_BASE_ADDR + 0x110) /*PLL Multiplier Control Register*/
#define PLL2_PREDIV (PLL2_BASE_ADDR + 0x114) /*PLL Pre-Divider control Register*/
#define PLL2_PLLDIV1 (PLL2_BASE_ADDR + 0x118) /*PLL Controller Div1 Register*/
#define PLL2_PLLDIV2 (PLL2_BASE_ADDR + 0x11C) /*PLL Controller Div2 Register*/
#define PLL2_PLLDIV3 (PLL2_BASE_ADDR + 0x120) /*PLL Controller Div3 Register*/
#define PLL2_OSCDIV1 (PLL2_BASE_ADDR + 0x124) /*Oscilator Divider Register*/
#define PLL2_POSTDIV (PLL2_BASE_ADDR + 0x128) /*PLL Post-Divider Register*/
#define PLL2_BPDIV (PLL2_BASE_ADDR + 0x12C) /*Bypass Divider Register*/
#define PLL2_WAKEUP (PLL2_BASE_ADDR + 0x130) /*Wakeup Register*/
#define PLL2_PLLCMD (PLL2_BASE_ADDR + 0x138) /*PLL Controller Command Register*/
#define PLL2_PLLSTAT (PLL2_BASE_ADDR + 0x13C) /*PLL Controller Status Register*/
#define PLL2_ALNCTL (PLL2_BASE_ADDR + 0x140) /*PLL Controller Clock Align Control Register*/
#define PLL2_DCHANGE (PLL2_BASE_ADDR + 0x144) /*PLLDiv Ratio Change status Register*/
#define PLL2_CKEN (PLL2_BASE_ADDR + 0x148) /*Clock Enable Control Register*/
#define PLL2_CKSTAT (PLL2_BASE_ADDR + 0x14C) /*Clock Status Register*/
#define PLL2_SYSTAT (PLL2_BASE_ADDR + 0x150) /*SYSCLK Status Register*/
menuitem "DM6467_PLL_Initialization";
/* System PLL Initialization in Normal mode with Clkin as the reference input */
hotmenu SystemPLL_NormalMode_ClkIn()
{
unsigned int i=0;
unsigned int GOSTAT;
unsigned int CLKSRC=1; /* CLKSRC=1 => External Clock
CLKSRC=0 => Onchip oscillator
*/
unsigned int PLL_INPUT=27; /* PLL input clock */
unsigned int PLL_MULTI=26; /* NORMAL MODE (27MHz x 27 = 729MHz) */
GEL_TextOut("Please wait System PLL initialization in Normal Mode is in Progress...Wait.....\n");
/* Select the Clock Mode as External Clock */
*(unsigned int*) PLL1_PLLCTL = *(unsigned int*) PLL1_PLLCTL | (CLKSRC<<8);
/* Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled through MMR */
*(unsigned int*) PLL1_PLLCTL = *(unsigned int*) PLL1_PLLCTL & 0xFFFFFFDF;
/* Set PLL Bypass Mode (Set PLLEN=0) */
*(unsigned int*) PLL1_PLLCTL = *(unsigned int*) PLL1_PLLCTL & 0xFFFFFFFE;
/* Wait for few cycles to allow PLLEN mux switches properly to bypass clock */
for(i=0; i<40; i++) {} /* 1 cycle : 27MHz (37ns) */
/* Wait : 37ns * 20 = 740(ns) */
/* Wait for few cycles to allow PLLEN Mux Switches */
/* properly to bypass clock */
/* Reset the PLL */
*(unsigned int*) PLL1_PLLCTL = *(unsigned int*) PLL1_PLLCTL | 0x8;
/* Disable the PLL */
*(unsigned int*) PLL1_PLLCTL = *(unsigned int*) PLL1_PLLCTL | 0x10;
/* --------------------------- */
/* PLL Initialization Sequence */
/* --------------------------- */
/* Power up the PLL */
*(unsigned int*) PLL1_PLLCTL = *(unsigned int*) PLL1_PLLCTL & 0xFFFFFFFD;
/* Enable the PLL from Disable Mode */
*(unsigned int*) PLL1_PLLCTL = *(unsigned int*) PLL1_PLLCTL & 0xFFFFFFEF;
for(i=0; i<4196; i++) {} /* Stabilization TIme : 150us */
/* 1 cycle : 1/27MHz */
/* Wait : 1/27MHz * 4096 = 151.7ns */
/* Set PLLM (x22) [Normal Mode] (27MHz x 22 = 594MHz) */
*(unsigned int*) PLL1_PLLM = PLL_MULTI;
/* ------------------------- */
/* Program PLLDIV Registers */
/* ------------------------- */
// Wait for pending (if any) GO command
GOSTAT = *(unsigned int*) PLL1_PLLSTAT & 0x1;
while(GOSTAT==1)
{
GOSTAT = *(unsigned int*) PLL1_PLLSTAT & 0x1;
}
// Set SYSCLK4 (ATA) Divider Value
*(unsigned int*)PLL1_PLLDIV4 = *(unsigned int*)PLL1_PLLDIV4 & 0xfffffff0;
*(unsigned int*)PLL1_PLLDIV4 |= 6; //ATA: 104.14MHz
// Set SYSCLK5 (TSIF0) Divider Value
*(unsigned int*)PLL1_PLLDIV5 = *(unsigned int*)PLL1_PLLDIV5 & 0xfffffff0;
*(unsigned int*)PLL1_PLLDIV5 |= 9; //TSIF0: 72.9MHz
// Set SYSCLK6 (TSIF1) Divider Value
*(unsigned int*)PLL1_PLLDIV6 = *(unsigned int*)PLL1_PLLDIV6 & 0xfffffff0;
*(unsigned int*)PLL1_PLLDIV6 |= 9; //TSIF1: 72.9MHz
// Set SYSCLK8 (VPIF) Divider Value
*(unsigned int*)PLL1_PLLDIV8 = *(unsigned int*)PLL1_PLLDIV8 & 0xfffffff0;
*(unsigned int*)PLL1_PLLDIV8 |= 9; //VPIF: 72.9MHz
// Set SYSCLK9 (VLYNQ) Divider Value
*(unsigned int*)PLL1_PLLDIV9 = *(unsigned int*)PLL1_PLLDIV9 & 0xfffffff0;
*(unsigned int*)PLL1_PLLDIV9 |= 6; //VLYNQ: 104.14MHz
*(unsigned int*) PLL1_PLLCMD |= 0x1;
// Let "GO" command finish
GOSTAT = *(unsigned int*) PLL1_PLLSTAT & 0x1;
while(GOSTAT==1)
{
GOSTAT = *(unsigned int*) PLL1_PLLSTAT & 0x1;
}
/* Wait min 32 cycles */
for(i=0; i<100; i++) {}
/* Bring PLL out of Reset */
*(unsigned int*) PLL1_PLLCTL = *(unsigned int*) PLL1_PLLCTL & 0xFFFFFFF7;
/* Wait for PLL to LOCK atleast 2000 MXI clock or Reference clock cycles */
for(i=0; i<3100; i++) {} /* Lock Time : 2000 cycles */
/* Allow 2000 Reference Clock to Lock */
/*Enable the PLL Bit of PLLCTL*/
*(unsigned int*) PLL1_PLLCTL = *(unsigned int*) PLL1_PLLCTL | 0x1;
GEL_TextOut("DONE: System PLL is Initialized at %d * %d = %dMHz\n",,,,,PLL_INPUT, (PLL_MULTI+1), (PLL_INPUT * (PLL_MULTI+1)));
}
/* DDR PLL Initialization in Normal mode with Clkin as the reference input */
hotmenu DDRPLL_NormalMode_ClkIn()
{
unsigned int i=0;
unsigned int CLKSRC=1; /* CLKSRC=1 => External Clock
CLKSRC=0 => Onchip oscillator
*/
unsigned int PLL_INPUT=27; /* PLL input clock */
unsigned int PLL_MULTI=22; /* DDR2 Clock = 27 * 23 = 621MHz */
GEL_TextOut("Pleae wait DDR PLL initialization in Normal Mode is in Progress...Wait.....\n");
/* Select the Clock Mode as External Clock */
*(unsigned int*) PLL2_PLLCTL = *(unsigned int*) PLL2_PLLCTL | (CLKSRC<<8);
/* Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled through MMR */
*(unsigned int*) PLL2_PLLCTL = *(unsigned int*) PLL2_PLLCTL & 0xFFFFFFDF;
/* Set PLL Bypass Mode (Set PLLEN=0) */
*(unsigned int*) PLL2_PLLCTL = *(unsigned int*) PLL2_PLLCTL & 0xFFFFFFFE;
/* Wait for few cycles to allow PLLEN mux switches properly to bypass clock */
for(i=0; i<40*11; i++) {} /* 1 cycle : 27MHz (37ns) */
/* Wait : 37ns * 20 = 740(ns) */
/* Wait for few cycles to allow PLLEN Mux Switches */
/* properly to bypass clock */
/* Reset the PLL */
*(unsigned int*) PLL2_PLLCTL = *(unsigned int*) PLL2_PLLCTL | 0x8;
/* Disable the PLL */
*(unsigned int*) PLL2_PLLCTL = *(unsigned int*) PLL2_PLLCTL | 0x10;
/* --------------------------- */
/* PLL Initialization Sequence */
/* --------------------------- */
/* Power up the PLL */
*(unsigned int*) PLL2_PLLCTL = *(unsigned int*) PLL2_PLLCTL & 0xFFFFFFFD;
/* Enable the PLL from Disable Mode */
*(unsigned int*) PLL2_PLLCTL = *(unsigned int*) PLL2_PLLCTL & 0xFFFFFFEF;
for(i=0; i<4196*11; i++) {} /* Stabilization TIme : 150us */
/* 1 cycle : 1/27MHz */
/* Wait : 1/27MHz * 4096 = 151.7ns */
/* Set PLLM (x22) [Normal Mode] (27MHz x 22 = 594MHz) */
*(unsigned int*) PLL2_PLLM = PLL_MULTI;
/* ------------------------- */
/* Program PLLDIV Registers */
/* ------------------------- */
/* No PLLDIV configuration needed */
/* Wait min 32 cycles */
for(i=0; i<100*11; i++) {}
/* Bring PLL out of Reset */
*(unsigned int*) PLL2_PLLCTL = *(unsigned int*) PLL2_PLLCTL & 0xFFFFFFF7;
/* Wait for PLL to LOCK atleast 2000 MXI clock or Reference clock cycles */
for(i=0; i<3100*11; i++) {} /* Lock Time : 2000 cycles */
/* Allow 2000 Reference Clock to Lock */
/*Enable the PLL Bit of PLLCTL*/
*(unsigned int*) PLL2_PLLCTL = *(unsigned int*) PLL2_PLLCTL | 0x1;
GEL_TextOut("DONE: DDR PLL is Initialized at %d * %d = %dMHz\n",,,,,PLL_INPUT, (PLL_MULTI+1), (PLL_INPUT * (PLL_MULTI+1)));
}
StartUp(){
SystemPLL_NormalMode_ClkIn();
DDRPLL_NormalMode_ClkIn();
DDR2ClkTurnOn();
DDR32bitInit_310_5MHZ();
}
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