📄 davincihd_arm_si_729mhz.gel.txt
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/* ---------------------------------------------------------------
* TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
* Created 2008, (C) Copyright 2008 Texas Instruments. All rights reserved
*
* ARM GEL File for 729MHz TMS320DM6467.
*
* ---------------------------------------------------------------*/
#define ARM_RAM0_I_MEM 0x00000004
#define ARM_RAM1_I_MEM 0x00004004
#define ARM_RAM0_D_MEM 0x00010004
#define ARM_RAM1_D_MEM 0x00014004
#define DSP_L2RAM_MEM 0x11818000
#define DSP_L1P_RAM_MEM 0x11E00000
#define DSP_L1D_RAM_MEM 0x11F00000
#define AEMIF_DATA_CS2_MEM 0x42000000
#define AEMIF_DATA_CS3_MEM 0x44000000
#define AEMIF_DATA_CS4_MEM 0x46000000
#define AEMIF_DATA_CS5_MEM 0x48000000
#define DDR_MEM 0x80000000
#define AEMIF_ADDR 0x20008000
#define RCSR (AEMIF_ADDR + 0x00) //Revision Code and Status Register
#define WAITCFG (AEMIF_ADDR + 0x04) //Async Wait Cycle Config Register
#define ACFG2 (AEMIF_ADDR + 0x10) //Async Bank1 Config Register
#define ACFG3 (AEMIF_ADDR + 0x14) //Async Bank2 Config Register
#define ACFG4 (AEMIF_ADDR + 0x18) //Async Bank3 Config Register
#define ACFG5 (AEMIF_ADDR + 0x1C) //Async Bank4 Config Register
#define AINTRAW (AEMIF_ADDR + 0x40) //Interrpt Raw Register
#define AINTMASK (AEMIF_ADDR + 0x44) //Interrupt Masked Register
#define AINTMASKSET (AEMIF_ADDR + 0x48) //Interrupt Mask Set Register
#define INTMASKCLEAR (AEMIF_ADDR + 0x4C) //Interrupt Mask Clear Register
#define NANDCTL (AEMIF_ADDR + 0x60) //NAND Flash Control Register
#define NANDSTAT (AEMIF_ADDR + 0x64) //NAND Flash Status Register
#define NANDECC2 (AEMIF_ADDR + 0x70) //NAND Flash 1 ECC Register
#define NANDECC3 (AEMIF_ADDR + 0x74) //NAND Flash 2 ECC Register
#define NANDECC4 (AEMIF_ADDR + 0x78) //NAND Flash 3 ECC Register
#define NANDECC5 (AEMIF_ADDR + 0x7C) //NAND Flash 4 ECC Register
#define DDR_BASE 0x20000000
#define EIDRR (DDR_BASE + 0x00) //EMIF Module ID and Revision Register
#define SDSTAT (DDR_BASE + 0x04) //SDRAM Status Register
#define SDCFG (DDR_BASE + 0x08) //SDRAM Bank Config Register
#define SDREF (DDR_BASE + 0x0C) //SDRAM Refresh Control Register
#define SDTIM0 (DDR_BASE + 0x10) //SDRAM Timing Register
#define SDTIM1 (DDR_BASE + 0x14) //SDRAM Timing Register
#define VBUSP (DDR_BASE + 0x20) //VBUSM Burst Priority Register
#define PERFCNT1 (DDR_BASE + 0x40) //Performance Counter Register 1
#define PERFCNT2 (DDR_BASE + 0x44) //Performance Counter Register 2
#define PERFCNTCFG (DDR_BASE + 0x48) //Performance Counter Config Register
#define PERFCNTMSTREGSEL (DDR_BASE + 0x4C) //Performance Counter Master Region Select Register
#define INTRAW (DDR_BASE + 0xC0) //Interrupt Raw Register
#define INTMASK (DDR_BASE + 0xC4) //Interrupt Masked Register
#define INTMASKSET (DDR_BASE + 0xC8) //Interrupt Mask Set Register
#define INTMASKCLR (DDR_BASE + 0xCC) //Interrupt Mask Clear Register
#define DDRPHYREV (DDR_BASE + 0xE0) //DDR PHY ID and Revision Register
#define DDRCTL1 (DDR_BASE + 0xE4) //DDR PHY Control 1 Register
#define DDRCTL2 (DDR_BASE + 0xE8) //DDR PHY Control 2 Register
#define DDRCTL3 (DDR_BASE + 0xEC) //DDR PHY Control 3 Register
#define VTPIOCTL (DDR_BASE + 0xF0) //VTP IO Control register
#define VTPIOSTAT (DDR_BASE + 0xF4) //VTP IO Status register
// System Module Registers
#define SYSTEM_MODULE_BASE_ADDR 0x01C40000
#define PINMUX0 (SYSTEM_MODULE_BASE_ADDR + 0x00)
#define DSP_BOOT_ADDR_REG (SYSTEM_MODULE_BASE_ADDR + 0x08)
#define HDVICPBOOT_REG (SYSTEM_MODULE_BASE_ADDR + 0x2C)
#define VDD3P3VPWDN_REG (SYSTEM_MODULE_BASE_ADDR + 0x48)
#define DSP_BOOT_ADDR 0x11818000
//PSC DDR
#define LPSC_DDR_EMIF 20 /* DDR_EMIF LPSC */
#define LPSC_AEMIF 21 /* AEMIF LPSC */
#define LPSC_DSP 1 /* DSP LPSC */
#define LPSC_HDVICP0 2 /* HDVICP0 LPSC */
#define LPSC_HDVICP1 3 /* HDVICP1 LPSC */
#define PSC_BASE_ADDR 0x01C41000
#define EPCPR (PSC_BASE_ADDR+0x070)
#define PTCMD (PSC_BASE_ADDR+0x120)
#define PTSTAT (PSC_BASE_ADDR+0x128)
#define PDSTAT (PSC_BASE_ADDR+0x200)
#define PDCTL (PSC_BASE_ADDR+0x300)
#define MDSTAT_DDR (PSC_BASE_ADDR+0x800+4*LPSC_DDR_EMIF)
#define MDCTL_DDR (PSC_BASE_ADDR+0xA00+4*LPSC_DDR_EMIF)
#define MDSTAT_AEMIF (PSC_BASE_ADDR+0x800+4*LPSC_AEMIF)
#define MDCTL_AEMIF (PSC_BASE_ADDR+0xA00+4*LPSC_AEMIF)
#define MDSTAT_DSP (PSC_BASE_ADDR+0x800+4*LPSC_DSP)
#define MDCTL_DSP (PSC_BASE_ADDR+0xA00+4*LPSC_DSP)
#define MDSTAT_HDVICP0 (PSC_BASE_ADDR+0x800+4*LPSC_HDVICP0)
#define MDCTL_HDVICP0 (PSC_BASE_ADDR+0xA00+4*LPSC_HDVICP0)
#define MDSTAT_HDVICP1 (PSC_BASE_ADDR+0x800+4*LPSC_HDVICP1)
#define MDCTL_HDVICP1 (PSC_BASE_ADDR+0xA00+4*LPSC_HDVICP1)
#define CSL_PSC_MDCTL_NEXT_MASK (0x0000001Fu)
#define CSL_PSC_MDCTL_NEXT_SHIFT (0x00000000u)
menuitem "DM6467_arm";
/*Bring DSP CPU out of Reset, Run from ARM*/
hotmenu BringDSPOutOfReset() {
/*Release the DSP Reset*/
*(unsigned int*) MDCTL_DSP = *(unsigned int*) MDCTL_DSP | 0x100;
GEL_TextOut("DSP CPU is Out of Reset \n");
}
hotmenu PutDSPInReset() {
/* Reset DSP */
*(unsigned int*) MDCTL_DSP = *(unsigned int*) MDCTL_DSP & 0x0FF;
GEL_TextOut("DSP CPU is in Reset Mode\n");
}
/* Bring HDVICP0 out of Reset */
BringHDVICP0OutOfReset() {
/* Enable HDVICP0 LPSC */
lpscEnable(LPSC_HDVICP0);
/* Release the HDVICP0 Reset */
*(unsigned int*) MDCTL_HDVICP0 = *(unsigned int*) MDCTL_HDVICP0 | 0x100;
GEL_TextOut("HDVICP0 is Out of Reset \n");
}
hotmenu PutHDVICP0InReset() {
/* Reset HDVICP0 */
*(unsigned int*) MDCTL_HDVICP0 = *(unsigned int*) MDCTL_HDVICP0 & 0x0FF;
GEL_TextOut("HDVICP0 is in Reset Mode\n");
}
/* Bring HDVICP1 out of Reset */
BringHDVICP1OutOfReset() {
/* Enable HDVICP1 LPSC */
lpscEnable(LPSC_HDVICP1);
/* Release the HDVICP1 Reset */
*(unsigned int*) MDCTL_HDVICP1 = *(unsigned int*) MDCTL_HDVICP1 | 0x100;
GEL_TextOut("HDVICP1 is Out of Reset \n");
}
hotmenu PutHDVICP1InReset() {
/* Reset HDVICP1 */
*(unsigned int*) MDCTL_HDVICP1 = *(unsigned int*) MDCTL_HDVICP1 & 0x0FF;
GEL_TextOut("HDVICP1 is in Reset Mode\n");
}
hotmenu DSPBootFromL2ByARM() {
unsigned int PdNum = 0, k=0, domainOn = 0;
/*Program the DSP Boot Address*/
*(unsigned int*) DSP_BOOT_ADDR_REG = DSP_BOOT_ADDR;
*(unsigned int*) MDCTL_DSP = *(unsigned int*) MDCTL_DSP | 0x3;
/* Make sure Power Domain 0 (Always On) is ON */
domainOn = (*(unsigned int*) PDSTAT) & 0x00000001;
if(domainOn == 0)
{
GEL_TextOut("ERR: Power Domain 0 is not ON\n");
}
*(unsigned int*) PTCMD = (1<<PdNum);
while(! (((*(unsigned int*)PTSTAT >> PdNum) & 0x00000001) == 0));
while(!((*(unsigned int*)MDSTAT_DSP & 0x0000001F) == 0x3));
/*Branch to itself*/
GEL_MemoryFill(DSP_BOOT_ADDR, 0, 0x20, 0x13);
/* Release the DSP Reset */
*(unsigned int*) MDCTL_DSP = *(unsigned int*) MDCTL_DSP | 0x100;
GEL_TextOut("DSP is Booted from L2RAM by ARM in Host Boot\n");
}
//This routine enables a module (provides clocks)
lpscEnable(lpscNum) {
unsigned int lpscMdctl = 0, lpscMdstat = 0, PdNum = 0/* Domain0 */, mdCtlVal=0;
/* Calculate MDCTL and MDSTAT reg addresses of the given LPSC */
lpscMdstat = (PSC_BASE_ADDR + 0x800) + 4 * lpscNum;
lpscMdctl = (PSC_BASE_ADDR + 0xA00) + 4 * lpscNum;
// Set NEXT = 0x3 to enable LPSC Module
mdCtlVal = *(unsigned int*)lpscMdctl;
*(unsigned int*) lpscMdctl = (mdCtlVal & ~CSL_PSC_MDCTL_NEXT_MASK) |
((0x3 << CSL_PSC_MDCTL_NEXT_SHIFT) & CSL_PSC_MDCTL_NEXT_MASK);
// Program goctl to start transition sequence for LPSCs
*(unsigned int*) PTCMD = (1 << PdNum);
// Wait for GOSTAT = NO TRANSITION from LPSC
while(! (((*(unsigned int*)PTSTAT >> PdNum) & 0x00000001) == 0));
// Wait for MODSTAT = ENABLE from LPSC
while(!((*(unsigned int*)lpscMdstat & 0x0000001F) == 0x3));
// GEL_TextOut("Enabled LPSC Module = %d\n",,,,,lpscNum);
}
//This routine disables a module (gates clocks)
lpscDisable(lpscNum) {
unsigned int lpscMdctl = 0, lpscMdstat = 0, PdNum = 0/* Domain0 */, mdCtlVal=0;
/* Calculate MDCTL and MDSTAT reg addresses of the given LPSC */
lpscMdstat = (PSC_BASE_ADDR + 0x800) + 4 * lpscNum;
lpscMdctl = (PSC_BASE_ADDR + 0xA00) + 4 * lpscNum;
// Set NEXT = 0x2 to disable LPSC Module
mdCtlVal = *(unsigned int*)lpscMdctl;
*(unsigned int*) lpscMdctl = (mdCtlVal & ~CSL_PSC_MDCTL_NEXT_MASK) |
((0x2 << CSL_PSC_MDCTL_NEXT_SHIFT) & CSL_PSC_MDCTL_NEXT_MASK);
// Program goctl to start transition sequence for LPSCs
*(unsigned int*) PTCMD = (1 << PdNum);
// Wait for GOSTAT = NO TRANSITION from LPSC
while(! (((*(unsigned int*)PTSTAT >> PdNum) & 0x00000001) == 0));
// Wait for MODSTAT = ENABLE from LPSC
while(!((*(unsigned int*)lpscMdstat & 0x0000001F) == 0x2));
// GEL_TextOut("Disabled LPSC Module = %d\n",,,,,lpscNum);
}
lpscSyncReset(lpscNum) {
unsigned int lpscMdctl = 0, lpscMdstat = 0, PdNum = 0/* Domain0 */, mdCtlVal=0;
/* Calculate MDCTL and MDSTAT reg addresses of the given LPSC */
lpscMdstat = (PSC_BASE_ADDR + 0x800) + 4 * lpscNum;
lpscMdctl = (PSC_BASE_ADDR + 0xA00) + 4 * lpscNum;
// Set NEXT = 0x1 to sync reset LPSC Module
mdCtlVal = *(unsigned int*)lpscMdctl;
*(unsigned int*) lpscMdctl = (mdCtlVal & ~CSL_PSC_MDCTL_NEXT_MASK) |
((0x1 << CSL_PSC_MDCTL_NEXT_SHIFT) & CSL_PSC_MDCTL_NEXT_MASK);
// Program goctl to start transition sequence for LPSCs
*(unsigned int*) PTCMD = (1 << PdNum);
// Wait for GOSTAT = NO TRANSITION from LPSC
while(! (((*(unsigned int*)PTSTAT >> PdNum) & 0x00000001) == 0));
// Wait for MODSTAT = ENABLE from LPSC
while(!((*(unsigned int*)lpscMdstat & 0x0000001F) == 0x1));
// GEL_TextOut("Sync Reset LPSC Module = %d\n",,,,,lpscNum);
}
/* This function powers up 3.3V I/O cells of all modules */
hotmenu VDD_3P3V_PowerUp()
{
/* Power up 3.3V I/O cells of all modules */
*(unsigned int*)VDD3P3VPWDN_REG = 0x0;
GEL_TextOut("Powered up 3.3V I/O cells of all modules.\n");
}
// Enable all LPSC modules
hotmenu lpscEnableAll() {
unsigned int lpscNum = 0;
unsigned int lpsc_start = 0;
unsigned int lpsc_end = 35; /* Skip locked LPSCs [36-44] */
GEL_TextOut("All LPSC Modules are getting enabled...Wait...\n");
/* Enable all LPSC modules */
for(lpscNum = lpsc_start; lpscNum <= lpsc_end; lpscNum++) {
lpscEnable(lpscNum);
}
GEL_TextOut("Skip locked LPSCs [36-44].\n");
lpscEnable(45); /* AINTC - Last LPSC(45) in the list */
GEL_TextOut("DONE: All LPSC Modules are Enabled.\n");
/* Power up 3.3V I/O cells of all modules */
VDD_3P3V_PowerUp();
}
hotmenu EnableHDVICP0_1()
{
unsigned int delay;
GEL_TextOut("Enabling HDVICP0 and HDVICP1...Wait...\n");
// First bring HDVICP0 and HDVICP1 out of reset.
BringHDVICP0OutOfReset();
BringHDVICP1OutOfReset();
/* Enable IAHB Fetch and Internal TCM */
*(unsigned int *) (HDVICPBOOT_REG) = 0x00100010;
/* Reset HDVICP0 */
lpscSyncReset(LPSC_HDVICP0);
lpscEnable(LPSC_HDVICP0);
/* Reset HDVICP1 */
lpscSyncReset(LPSC_HDVICP1);
lpscEnable(LPSC_HDVICP1);
GEL_TextOut("DONE: Enabled HDVICP0 and HDVICP1\n");
}
menuitem "DM6467 DDR Configuration";
hotmenu DDR2ClkTurnOn()
{
unsigned int PdNum = 0, domainOn = 0;
*(unsigned int*) MDCTL_DDR = *(unsigned int*) MDCTL_DDR | 0x3;
/* Make sure Power Domain 0 (Always On) is ON */
domainOn = (*(unsigned int*) PDSTAT) & 0x00000001;
if(domainOn == 0)
{
GEL_TextOut("ERR: Power Domain 0 is not ON\n");
}
*(unsigned int*) PTCMD = (1<<PdNum);
while(! (((*(unsigned int*)PTSTAT >> PdNum) & 0x00000001) == 0));
while(!((*(unsigned int*)MDSTAT_DDR & 0x0000001F) == 0x3));
// DDR VTP Initialization
// VTPIOCR = 0x00000002; // VTPIOCR register default value. VTP is powered up in dynamic update mode.
*(unsigned int*) VTPIOCTL = 0x00000003; // Set VTP_RECAL bit.
*(unsigned int*) VTPIOCTL = 0x00000002; // Toggle VTP_RECAL bit.
// Wait for completion of VTP calibration and DDLL ready.
while(!((*(unsigned int*)SDSTAT & 0x00000004) == 0x04)); // Wait for phy_dll_ready/PHYRDY bit set.
lpscSyncReset(LPSC_DDR_EMIF);
lpscEnable(LPSC_DDR_EMIF);
GEL_TextOut("DDR2 Controller Clocks are Turned On and VTP initializaion Done\n");
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