📄 arm gel file davincihd_arm.gel.txt
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* Setup_Pin_Mux( ) *
* Configure Pin Multiplexing *
* *
* ------------------------------------------------------------------------ */
hotmenu
Setup_Pin_Mux( )
{
int pcien;
#define PINMUX0 *( unsigned int* )( 0x01c40000 )
#define PINMUX1 *( unsigned int* )( 0x01c40004 )
#define VDD3P3V_PWDN *( unsigned int* )( 0x01c40048 )
GEL_TextOut( "Setup PinMux... " );
pcien = ( PINMUX0 & ( 1 << 2 ) );
/*
* PinMux settings for:
* [Normal Operation]
*/
if ( pcien == 0 )
{
PINMUX0 = 0x00000001;
/* | ( 0 << 31 ) // VBUSDIS [USB_DRVVBUS]
| ( 0 << 30 ) // STCCK [GPIO4]
| ( 0 << 29 ) // AUDCK1 [GPIO2]
| ( 0 << 28 ) // AUDCK0 [GPIO3]
| ( 0 << 24 ) // [2]CRGMUX [no CRGEN]
| ( 0 << 22 ) // [2]TSSOMUX [VP_DOUT[11:8]]
| ( 0 << 20 ) // [2]TSSIMUX [VP_DIN[7:0]]
| ( 0 << 18 ) // [2]PTSOMUX [VP_DIN[7:0]]
| ( 0 << 16 ) // [2]PTSIMUX [VP_DIN[15:8]]
| ( 0 << 5 ) // PINTD [GPIO5]
| ( 0 << 2 ) // PCIEN [no PCI]
| ( 0 << 1 ) // HPIEN [no HPI]
| ( 1 << 0 ); // ATAEN [ATA/NAND]*/
PINMUX1 = 0x0000002d;
/* | ( 2 << 4 ) // [2]UART2CTL [IrDA]
| ( 3 << 2 ) // [2]UART1CTL [GPIO]
| ( 1 << 0 ); // [2]UART0CTL [UART0 w/o Flow]*/
}
/*
* PinMux settings for:
* [PCI Operation]
*/
else
{
PINMUX0 = 0x00000024;
/* | ( 0 << 31 ) // VBUSDIS [USB_DRVVBUS]
| ( 0 << 30 ) // STCCK [GPIO4]
| ( 0 << 29 ) // AUDCK1 [GPIO2]
| ( 0 << 28 ) // AUDCK0 [GPIO3]
| ( 0 << 24 ) // [2]CRGMUX [no CRGEN]
| ( 0 << 22 ) // [2]TSSOMUX [VP_DOUT[11:8]]
| ( 0 << 20 ) // [2]TSSIMUX [VP_DIN[7:0]]
| ( 0 << 18 ) // [2]PTSOMUX [VP_DIN[7:0]]
| ( 0 << 16 ) // [2]PTSIMUX [VP_DIN[15:8]]
| ( 1 << 5 ) // PINTD [PINTD]
| ( 1 << 2 ) // PCIEN [PCI]
| ( 0 << 1 ) // HPIEN [no HPI]
| ( 0 << 0 ); // ATAEN [no ATA]*/
PINMUX1 = 0x0000002d;
/* | ( 2 << 4 ) // [2]UART2CTL [IrDA]
| ( 3 << 2 ) // [2]UART1CTL [GPIO]
| ( 1 << 0 ); // [2]UART0CTL [UART0 w/o Flow]*/
}
/* 3.3V Power Domain */
VDD3P3V_PWDN = 0x180000c0;
/* | ( 1 << 28 ) // USBV [Power Down][-> USB +5V]
| ( 1 << 27 ) // CLKOUT [Power Down][-> DC_P2]
| ( 0 << 25 ) // SPI [Power Up]
| ( 0 << 24 ) // VLYNQ [Power Up]
| ( 0 << 21 ) // GMII [Power Up]
| ( 0 << 20 ) // MII [Power Up]
| ( 0 << 19 ) // McASP1 [Power Up]
| ( 0 << 18 ) // McASP0 [Power Up]
| ( 0 << 17 ) // PCIHPI1 [Power Up]
| ( 0 << 16 ) // PCIHPI0 [Power Up]
| ( 0 << 15 ) // GPIO [Power Up]
| ( 0 << 14 ) // WDTIM [Power Up]
| ( 0 << 13 ) // TIM23 [Power Up]
| ( 0 << 12 ) // TIM01 [Power Up]
| ( 0 << 11 ) // PWM1 [Power Up]
| ( 0 << 10 ) // PWM0 [Power Up]
| ( 0 << 9 ) // UR2FC [Power Up]
| ( 0 << 8 ) // UR2DAT [Power Up]
| ( 1 << 7 ) // UR1FC [Power Down]
| ( 1 << 6 ) // UR1DAT [Power Down]
| ( 0 << 5 ) // UR0MDM [Power Up]
| ( 0 << 4 ) // UR0DF [Power Up]
| ( 0 << 3 ) // VPIF3 [Power Up]
| ( 0 << 2 ) // VPIF2 [Power Up]
| ( 0 << 1 ) // VPIF1 [Power Up]
| ( 0 << 0 ); // VPIF0 [Power Up]*/
GEL_TextOut( "[Done]\n" );
}
/* ------------------------------------------------------------------------ *
* *
* Setup_Psc_All_On( ) *
* Enable all PSC modules on ALWAYSON and DSP power dominas. *
* *
* ------------------------------------------------------------------------ */
hotmenu
Setup_Psc_All_On( )
{
int i;
GEL_TextOut( "Setup Power Modules (All on)... " );
/*
* Enable all non-reserved power modules
* Reserved: 36-44
*/
for ( i = 1 ; i <= 35 ; i++ )
psc_change_state( i , 3 );
i = 45;
psc_change_state( i , 3 );
GEL_TextOut( "[Done]\n" );
}
/* ------------------------------------------------------------------------ *
* *
* psc_change_state( id, state ) *
* id = Domain #ID *
* state = ( ENABLE, DISABLE, SYNCRESET, RESET ) *
* ( =3 , =2 , =1 , =0 ) *
* *
* ------------------------------------------------------------------------ */
psc_change_state( int id, int state )
{
#define PSC_PTCMD *( unsigned int* )( 0x01c41120 )
#define PSC_PTSTAT *( unsigned int* )( 0x01c41128 )
unsigned int* mdstat = ( unsigned int* )( 0x01c41800 + ( 4 * id ) );
unsigned int* mdctl = ( unsigned int* )( 0x01c41a00 + ( 4 * id ) );
/*
* Step 0 - Ignore request if the state is already set as is
*/
if ( ( *mdstat & 0x001f ) == state )
return;
/*
* Step 1 - Wait for PTSTAT.GOSTAT to clear
*/
while( PSC_PTSTAT & 1 );
/*
* Step 2 - Set MDCTLx.NEXT to new state
*/
*mdctl &= ~0x1f;
*mdctl |= state;
/*
* Step 3 - Start power transition ( set PTCMD.GO to 1 )
*/
PSC_PTCMD = 1;
/*
* Step 4 - Wait for PTSTAT.GOSTAT to clear
*/
while( PSC_PTSTAT & 1 );
/*
* Step 5 - Verify state changed
*/
while( ( *mdstat & 0x001f ) != state );
}
/* ------------------------------------------------------------------------ *
* *
* setup_pll_0( ) *
* *
* clock_source <- 0: Onchip Oscillator *
* 1: External Clock *
* *
* pll_mult <- 21: 22x Multiplier * 27MHz Clk = 594 MHz *
* *
* ------------------------------------------------------------------------ */
setup_pll_0( int clock_source, int pll_mult )
{
unsigned int* pll_ctl = ( unsigned int* )( 0x01c40900 );
unsigned int* pll_pllm = ( unsigned int* )( 0x01c40910 );
unsigned int* pll_cmd = ( unsigned int* )( 0x01c40938 );
unsigned int* pll_postdiv = ( unsigned int* )( 0x01c40928 );
unsigned int* pll_bpdiv = ( unsigned int* )( 0x01c4092c );
unsigned int* pll_div1 = ( unsigned int* )( 0x01c40918 );
unsigned int* pll_div2 = ( unsigned int* )( 0x01c4091c );
unsigned int* pll_div3 = ( unsigned int* )( 0x01c40920 );
unsigned int* pll_div4 = ( unsigned int* )( 0x01c40960 );
unsigned int* pll_div5 = ( unsigned int* )( 0x01c40964 );
unsigned int* pll_div6 = ( unsigned int* )( 0x01c40968 );
unsigned int* pll_div7 = ( unsigned int* )( 0x01c4096c );
unsigned int* pll_div8 = ( unsigned int* )( 0x01c40970 );
unsigned int* pll_div9 = ( unsigned int* )( 0x01c40974 );
int pll0_freq = 27 * ( pll_mult + 1 );
int dsp_freq = pll0_freq;
int arm_freq = pll0_freq / 2;
int postdiv = 0;
int bpdiv = 0;
GEL_TextOut( "Setup PLL0 " );
/*
* Step 1 - Set clock mode
*/
if ( clock_source == 0 )
*pll_ctl &= ~0x0100; // Onchip Oscillator
else
*pll_ctl |= 0x0100; // External Clock
/*
* Step 2 - Set PLL to bypass
* - Wait for PLL to stabilize
*/
*pll_ctl &= ~0x0020;
*pll_ctl &= ~0x0001;
_wait( 150 );
/*
* Step 3 - Reset PLL
*/
*pll_ctl |= 0x0008;
/*
* Step 4 - Disable PLL
* Step 5 - Powerup PLL
* Step 6 - Enable PLL
* Step 7 - Wait for PLL to stabilize
*/
*pll_ctl |= 0x0010; // Disable PLL
*pll_ctl &= ~0x0002; // Power up PLL
*pll_ctl &= ~0x0010; // Enable PLL
_wait( 150 ); // Wait for PLL to stabilize
/*
* Step 8 - Load PLL multiplier
*/
*pll_pllm = pll_mult & 0x3f;
/*
* Step 9 - Set PLL post dividers
* Div1: (Fixed @ /1)DSP
* Div2: (Fixed @ /2)ARM/PCI/GraphicsEngine/HD-VICP0-1/EDMA/SCR
* Div3: (Fixed @ /4)Peripherals
* Div4: ATA
* Div5: SYSCLK5
* Div6: SYSCLK6
* Div7: SYSCLK7
* Div8: VIDEO
* Div9: VLYNQ
*/
*pll_div1 = 0x8000 | 0; // DSP
*pll_div2 = 0x8000 | 1; // ARM/PCI/HDVICP
*pll_div3 = 0x8000 | 3; // Peripherals
*pll_div4 = 0x8000 | 5; // ATA divider
//*pll_div5 = 0x8000 | 7;
//*pll_div6 = 0x8000 | 7;
//*pll_div7 = 0x8000 | 7;
*pll_div8 = 0x8000 | 7; // Video Clock
*pll_div9 = 0x8000 | 5; // VLYNQ divider
//*pll_bpdiv = 0x8000 | bpdiv; // Bypass divider
//*pll_postdiv= 0x8000 | postdiv; // Post divider
*pll_cmd |= 0x0001; // GO
_wait( 2000 );
/*
* Step 10 - Wait for PLL to reset ( 2000 cycles )
* Step 11 - Release from reset
*/
_wait( 2000 );
*pll_ctl &= ~0x0008;
/*
* Step 12 - Wait for PLL to re-lock ( 2000 cycles )
* Step 13 - Switch out of BYPASS mode
*/
_wait( 2000 );
*pll_ctl |= 0x0001;
pll0_freq = 27 * ( ( *pll_pllm & 0x3f ) + 1 );
dsp_freq = pll0_freq;
arm_freq = pll0_freq / 2;
GEL_TextOut( "(DSP = %d MHz + ",,,,, dsp_freq );
GEL_TextOut( "ARM = %d MHz + ",,,,, arm_freq );
if ( clock_source == 0 )
GEL_TextOut( "Onchip Oscillator)... " );
else
GEL_TextOut( "External Clock)... " );
GEL_TextOut( "[Done]\n" );
}
hotmenu
Setup_Pll0_594_MHz_OscIn( )
{
/* DSP @ [594 MHz] & ARM @ [297 MHz] w/ Onchip Oscillator */
setup_pll_0( 0, 21 );
}
/* ------------------------------------------------------------------------ *
* *
* setup_pll_1( ) *
* *
* clock_source <- 0: Onchip Oscillator *
* 1: External Clock *
* *
* pll_mult <- PLL Multiplier *
* 23: 24x Multiplier * 27MHz Clk = 648 MHz *
* *
* ddr2_div <- DDR2 divider ( For pll1 ) *
* 1: 648 MHz Clk / (2*2)x Divider = 162 MHz *
* *
* ------------------------------------------------------------------------ */
setup_pll_1( int clock_source, int pll_mult, int ddr2_div )
{
unsigned int* pll_ctl = ( unsigned int* )( 0x01c40d00 );
unsigned int* pll_pllm = ( unsigned int* )( 0x01c40d10 );
unsigned int* pll_cmd = ( unsigned int* )( 0x01c40d38 );
unsigned int* pll_stat = ( unsigned int* )( 0x01c40d3c );
unsigned int* pll_div1 = ( unsigned int* )( 0x01c40d18 );
unsigned int* pll_div2 = ( unsigned int* )( 0x01c40d1c );
unsigned int* pll_bpdiv = ( unsigned int* )( 0x01c40d2c );
int pll1_freq = 27 * ( pll_mult + 1 );
int ddr2_freq = pll1_freq / ( 2 * ( ddr2_div + 1 ) );
int bpdiv = 1;
GEL_TextOut( "Setup PLL1 " );
/*
* Step 0 - Stop all peripheral operations
*/
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