📄 arm gel file davincihd_arm.gel.txt
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/* ------------------------------------------------------------------------ *
* *
* davincihd_arm.gel *
* Version 0.99 *
* *
* This GEL file is designed to be used in conjunction with *
* CCStudio 3.2+ and the DM6467 based EVM. *
* *
* ------------------------------------------------------------------------ */
/* ------------------------------------------------------------------------ *
* *
* StartUp( ) *
* Setup Memory Map *
* *
* ------------------------------------------------------------------------ */
StartUp( )
{
Setup_Memory_Map( );
}
/* ------------------------------------------------------------------------ *
* *
* OnTargetConnect( ) *
* Setup PinMux, Power, PLLs, DDR, & EMIF *
* *
* ------------------------------------------------------------------------ */
OnTargetConnect( )
{
GEL_TextOut( "\nDaVinci HD ARM Startup Sequence\n\n" );
Disable_IRQ_Flush_Cache( ); // Clean up system state
Enable_Instruction_Cache( ); // Enable I-Cache
Setup_Pin_Mux( ); // Setup Pin Mux
Setup_Psc_All_On( ); // Setup All Power Domains
Setup_Pll0_594_MHz_OscIn( ); // Setup Pll0 [DSP @ 594 MHz, ARM @ 297 MHz]
Setup_DDR_297_MHz( ); // Setup DDR2 [297 MHz]
Setup_EMIFCS2_NandFlash_8Bit( );// Setup NAND Flash
DSP_Boot_from_L2_ram( ); // Boot DSP from L2
GEL_TextOut( "\nStartup Complete.\n\n" );
}
/* ------------------------------------------------------------------------ *
* *
* OnPreFileLoaded( ) *
* This function is called automatically when the 'Load Program' *
* Menu item is selected. *
* *
* ------------------------------------------------------------------------ */
OnPreFileLoaded( )
{
/*
* GEL_Reset() is used to deal with the worst case senario of
* unknown target state. If for some reason a reset is not desired
* upon target connection, GEL_Reset() may be removed and replaced
* with something "less brutal" like a cache initialization
* function.
*/
GEL_Reset( );
Disable_VPSS( ); // Disable VPSS
Disable_IRQ_Flush_Cache( ); // Clean up system state
Disable_EDMA( ); // Disable EDMA
//Setup_DDR_297_MHz( ); // Setup DDR2 [297 MHz]
GEL_TextOut( "\n" );
}
/* ------------------------------------------------------------------------ *
* *
* OnRestart( ) *
* This function is called by CCS when you do Debug->Restart. *
* The goal is to put the ARM9 into a known good state with respect to *
* edma. *
* Failure to do this can cause problems when you restart and *
* run your application code multiple times. This is different *
* then OnPreFileLoaded() which will do a GEL_Reset() to get the *
* ARM9 into a known good state. *
* *
* ------------------------------------------------------------------------ */
OnRestart( int nErrorCode )
{
Disable_VPSS( ); // Disable VPSS
Disable_IRQ_Flush_Cache( ); // Clean up system state
Disable_EDMA( ); // Disable EDMA
GEL_TextOut( "\n" );
}
menuitem "DaVinci HD Memory Map";
/* ------------------------------------------------------------------------ *
* *
* Setup_Memory_Map( ) *
* Setup the Memory Map for ARM side only. *
* *
* ------------------------------------------------------------------------ */
hotmenu
Setup_Memory_Map( )
{
GEL_MapOn( );
GEL_MapReset( );
/* ARM RAM & ROM */
GEL_MapAddStr( 0x00000000, 0, 0x00004000, "R|W|AS4", 0 ); // ARM RAM0 Instruction
GEL_MapAddStr( 0x00004000, 0, 0x00004000, "R|W|AS4", 0 ); // ARM RAM1 Instruction
GEL_MapAddStr( 0x00008000, 0, 0x00004000, "R|AS4", 0 ); // ARM ROM Instruction
GEL_MapAddStr( 0x00010000, 0, 0x00004000, "R|W|AS4", 0 ); // ARM RAM0 Data
GEL_MapAddStr( 0x00014000, 0, 0x00004000, "R|W|AS4", 0 ); // ARM RAM1 Data
GEL_MapAddStr( 0x00018000, 0, 0x00008000, "R|AS4", 0 ); // ARM ROM Data
/* Extend Trace */
GEL_MapAddStr( 0x01bc0000, 0, 0x00001900, "R|W|AS4", 0 ); // ARM ETB
/* Peripherals */
GEL_MapAddStr( 0x01c00000, 0, 0x00000644, "R|W|AS4", 0 ); // EDMA Channel Ctrl
GEL_MapAddStr( 0x01c01000, 0, 0x00000098, "R|W|AS4", 0 ); // EDMA Channel Ctrl
GEL_MapAddStr( 0x01c02000, 0, 0x00000098, "R|W|AS4", 0 ); // EDMA Channel Ctrl
GEL_MapAddStr( 0x01c02200, 0, 0x00000098, "R|W|AS4", 0 ); // EDMA Channel Ctrl
GEL_MapAddStr( 0x01c10000, 0, 0x000003d8, "R|W|AS4", 0 ); // EDMA Transfer Ctrl 0
GEL_MapAddStr( 0x01c10400, 0, 0x000003d8, "R|W|AS4", 0 ); // EDMA Transfer Ctrl 1
GEL_MapAddStr( 0x01c10800, 0, 0x000003d8, "R|W|AS4", 0 ); // EDMA Transfer Ctrl 2
GEL_MapAddStr( 0x01c10c00, 0, 0x000003d8, "R|W|AS4", 0 ); // EDMA Transfer Ctrl 3
GEL_MapAddStr( 0x01c12000, 0, 0x00000400, "R|W|AS4", 0 ); // Video Port
GEL_MapAddStr( 0x01c12800, 0, 0x00000800, "R|W|AS4", 0 ); // Graphics Engine
GEL_MapAddStr( 0x01c13000, 0, 0x00000400, "R|W|AS4", 0 ); // Stream I/O 0
GEL_MapAddStr( 0x01c13400, 0, 0x00000400, "R|W|AS4", 0 ); // Stream I/O 1
GEL_MapAddStr( 0x01c1a000, 0, 0x00000800, "R|W|AS4", 0 ); // PCI Control
GEL_MapAddStr( 0x01c20000, 0, 0x00000060, "R|W|AS4", 0 ); // UART 0
GEL_MapAddStr( 0x01c20400, 0, 0x00000060, "R|W|AS4", 0 ); // UART 1
GEL_MapAddStr( 0x01c20800, 0, 0x00000060, "R|W|AS4", 0 ); // UART 2
GEL_MapAddStr( 0x01c21000, 0, 0x0000003c, "R|W|AS4", 0 ); // I2C
GEL_MapAddStr( 0x01c21400, 0, 0x00000028, "R|W|AS4", 0 ); // Timer 0
GEL_MapAddStr( 0x01c21800, 0, 0x00000028, "R|W|AS4", 0 ); // Timer 1
GEL_MapAddStr( 0x01c21c00, 0, 0x0000002c, "R|W|AS4", 0 ); // Timer 2 WDT
GEL_MapAddStr( 0x01c22000, 0, 0x0000001c, "R|W|AS4", 0 ); // PWM 0
GEL_MapAddStr( 0x01c22400, 0, 0x0000001c, "R|W|AS4", 0 ); // PWM 1
GEL_MapAddStr( 0x01c26000, 0, 0x00000058, "R|W|AS4", 0 ); // CRGEN0
GEL_MapAddStr( 0x01c26400, 0, 0x00000058, "R|W|AS4", 0 ); // CRGEN1
GEL_MapAddStr( 0x01c40000, 0, 0x00000080, "R|W|AS4", 0 ); // Device System
GEL_MapAddStr( 0x01c40400, 0, 0x00000400, "R|W|AS4", 0 ); // Security Controller
GEL_MapAddStr( 0x01c40800, 0, 0x00000178, "R|W|AS4", 0 ); // PLL0
GEL_MapAddStr( 0x01c40c00, 0, 0x00000154, "R|W|AS4", 0 ); // PLL1
GEL_MapAddStr( 0x01c41000, 0, 0x00000518, "R|W|AS4", 0 ); // PSC Domain Control
GEL_MapAddStr( 0x01c41800, 0, 0x000000b8, "R|W|AS4", 0 ); // PSC Module Status
GEL_MapAddStr( 0x01c41a00, 0, 0x000000b8, "R|W|AS4", 0 ); // PSC Module Control
GEL_MapAddStr( 0x01c48000, 0, 0x00000050, "R|W|AS4", 0 ); // ARM Interrupts
GEL_MapAddStr( 0x01c64000, 0, 0x00002000, "R|W|AS4", 0 ); // USB 2.0
GEL_MapAddStr( 0x01c66000, 0, 0x0000007c, "R|W|AS2", 0 ); // ATA
GEL_MapAddStr( 0x01c66800, 0, 0x00000068, "R|W|AS4", 0 ); // SPI
GEL_MapAddStr( 0x01c67000, 0, 0x00000060, "R|W|AS4", 0 ); // GPIO
GEL_MapAddStr( 0x01c67800, 0, 0x00000800, "R|W|AS4", 0 ); // HPI
GEL_MapAddStr( 0x01c80000, 0, 0x0000028c, "R|W|AS4", 0 ); // EMAC Control
GEL_MapAddStr( 0x01c81000, 0, 0x00000078, "R|W|AS4", 0 ); // EMAC Module
GEL_MapAddStr( 0x01c82000, 0, 0x00002000, "R|W|AS4", 0 ); // EMAC Module RAM
GEL_MapAddStr( 0x01c84000, 0, 0x00000090, "R|W|AS4", 0 ); // MDIO
GEL_MapAddStr( 0x01d11000, 0, 0x00001400, "R|W|AS4", 0 ); // MCASP0
GEL_MapAddStr( 0x01d11400, 0, 0x00000400, "R|W|AS4", 0 ); // MCASP0 Data
GEL_MapAddStr( 0x01d11800, 0, 0x00000400, "R|W|AS4", 0 ); // MCASP1
GEL_MapAddStr( 0x01d11c00, 0, 0x00000400, "R|W|AS4", 0 ); // MCASP1 Data
GEL_MapAddStr( 0x02000000, 0, 0x00200000, "R|W|AS4", 0 ); // HD-VICP0
GEL_MapAddStr( 0x02200000, 0, 0x00200000, "R|W|AS4", 0 ); // HD-VICP1
/* HD-VICP0 */
GEL_MapAddStr( 0x11400000, 0, 0x00100000, "R|W|AS4", 0 ); // HD-VICP0
GEL_MapAddStr( 0x40400000, 0, 0x00040000, "R|W|AS4", 0 ); // HD-VICP0 R/W Port
GEL_MapAddStr( 0x40440000, 0, 0x00040000, "R|W|AS4", 0 ); // HD-VICP0 R-Only Port
GEL_MapAddStr( 0x40480000, 0, 0x00040000, "R|W|AS4", 0 ); // HD-VICP0 W-Only Port
/* HD-VICP1 */
GEL_MapAddStr( 0x11600000, 0, 0x00100000, "R|W|AS4", 0 ); // HD-VICP1
GEL_MapAddStr( 0x40600000, 0, 0x00040000, "R|W|AS4", 0 ); // HD-VICP1 R/W Port
GEL_MapAddStr( 0x40640000, 0, 0x00040000, "R|W|AS4", 0 ); // HD-VICP1 R-Only Port
GEL_MapAddStr( 0x40680000, 0, 0x00040000, "R|W|AS4", 0 ); // HD-VICP1 W-Only Port
/* DSP RAM */
GEL_MapAddStr( 0x11818000, 0, 0x00020000, "R|W|AS4", 0 ); // DSP L2 RAM/Cache
GEL_MapAddStr( 0x11e00000, 0, 0x00008000, "R|W|AS4", 0 ); // DSP L1P Cache/RAM
GEL_MapAddStr( 0x11f00000, 0, 0x00008000, "R|W|AS4", 0 ); // DSP L1D Cache/RAM
/* DDR2 */
GEL_MapAddStr( 0x20000000, 0, 0x000000f4, "R|W|AS4", 0 ); // DDR2 Control
GEL_MapAddStr( 0x80000000, 0, 0x40000000, "R|W|AS4", 0 ); // DDR2 SDRAM
/* EMIFA */
GEL_MapAddStr( 0x20008000, 0, 0x00000080, "R|W|AS4", 0 ); // EMIFA Control
GEL_MapAddStr( 0x42000000, 0, 0x02000000, "R|W|AS4", 0 ); // AEMIF CS2
GEL_MapAddStr( 0x44000000, 0, 0x02000000, "R|W|AS4", 0 ); // AEMIF CS3
GEL_MapAddStr( 0x46000000, 0, 0x02000000, "R|W|AS4", 0 ); // AEMIF CS4
GEL_MapAddStr( 0x48000000, 0, 0x02000000, "R|W|AS4", 0 ); // AEMIF CS5
/* VLYNQ */
GEL_MapAddStr( 0x20010000, 0, 0x00000048, "R|W|AS4", 0 ); // VLYNQ Control
//GEL_MapAddStr( 0x20010080, 0, 0x00000068, "R|W|AS4", 0 ); // VLYNQ Control Remote
GEL_MapAddStr( 0x4c000000, 0, 0x04000000, "R|W|AS4", 0 ); // VLYNQ Remote Devices
/* PCI */
GEL_MapAddStr( 0x30000000, 0, 0x10000000, "R|W|AS4", 0 ); // PCI Address Space
}
/* ------------------------------------------------------------------------ *
* *
* Clear_Memory_Map( ) *
* Clear the Memory Map *
* *
* ------------------------------------------------------------------------ */
hotmenu
Clear_Memory_Map( )
{
GEL_MapOff( );
GEL_MapReset( );
}
menuitem "DaVinci HD Functions";
_wait( int delay )
{
int i;
for( i = 0 ; i < delay ; i++ ){}
}
/* ------------------------------------------------------------------------ *
* *
* Flush_Cache_Disable_MMU( ) *
* Flush Cache & Disable MMU *
* *
* ------------------------------------------------------------------------ */
Disable_IRQ_Flush_Cache( )
{
#define INTC_FIQ0 *( unsigned int* )( 0x01c48000 )
#define INTC_FIQ1 *( unsigned int* )( 0x01c48004 )
#define INTC_IRQ0 *( unsigned int* )( 0x01c48008 )
#define INTC_IRQ1 *( unsigned int* )( 0x01c4800c )
#define INTC_EINT0 *( unsigned int* )( 0x01c48018 )
#define INTC_EINT1 *( unsigned int* )( 0x01c4801c )
#define INTC_INTCTL *( unsigned int* )( 0x01c48020 )
#define INTC_EABASE *( unsigned int* )( 0x01c48024 )
GEL_TextOut( "Disable IRQ/FIQ\n" );
CPSR = 0x400000d3; // Set to supervisor mode, disable IRQ/FIQ
GEL_TextOut( "Flush Cache\n" );
REG_CP15_FLSH_DI; // Flush then disable D-Cache & I-Cache
REG_CP15_I_CACHE = 0;
REG_CP15_D_CACHE = 0;
GEL_TextOut( "Disable MMU\n" );
REG_CP15_MMU = 0; // Disable MMU
INTC_INTCTL = 4; // Disable ARM interrupts
INTC_EABASE = 0;
INTC_EINT0 = 0;
INTC_EINT1 = 0;
INTC_FIQ0 = 0xffffffff;
INTC_FIQ1 = 0xffffffff;
INTC_IRQ0 = 0xffffffff;
INTC_IRQ1 = 0xffffffff;
_wait( 200 );
}
/* ------------------------------------------------------------------------ *
* *
* Disable_VPSS( ) *
* Disable VPFE & VPBE *
* *
* ------------------------------------------------------------------------ */
Disable_VPSS( )
{
#define VPIF_CHCTRL0 *( unsigned int* )( 0x01c12004 )
#define VPIF_CHCTRL1 *( unsigned int* )( 0x01c12008 )
#define VPIF_CHCTRL2 *( unsigned int* )( 0x01c1200c )
#define VPIF_CHCTRL3 *( unsigned int* )( 0x01c12010 )
#define VPIF_INTEN *( unsigned int* )( 0x01c12020 )
#define VPIF_INTENCLR *( unsigned int* )( 0x01c12028 )
GEL_TextOut( "Disable VPSS\n" );
VPIF_CHCTRL0 = 0;
VPIF_CHCTRL1 = 0;
VPIF_CHCTRL2 = 0;
VPIF_CHCTRL3 = 0;
VPIF_INTEN = 0;
VPIF_INTENCLR = 0x0f;
/* Clear Channels */
//GEL_MemoryFill( 0x01c12040, 0, 104, 0 ); // Channel 0-3
}
/* ------------------------------------------------------------------------ *
* *
* Disable_EDMA( ) *
* Disabe EDMA events and interrupts, clear any pending events *
* *
* ------------------------------------------------------------------------ */
Disable_EDMA( )
{
#define EDMA_3CC_IECRH *( unsigned int* )( 0x01c0105c )
#define EDMA_3CC_EECRH *( unsigned int* )( 0x01c0102c )
#define EDMA_3CC_ICRH *( unsigned int* )( 0x01c01074 )
#define EDMA_3CC_ECRH *( unsigned int* )( 0x01c0100c )
#define EDMA_3CC_IECR *( unsigned int* )( 0x01c01058 )
#define EDMA_3CC_EECR *( unsigned int* )( 0x01c01028 )
#define EDMA_3CC_ICR *( unsigned int* )( 0x01c01070 )
#define EDMA_3CC_ECR *( unsigned int* )( 0x01c01008 )
GEL_TextOut( "Disable EDMA events\n" );
EDMA_3CC_IECRH = 0xffffffff; // IERH - Disable high interrupts
EDMA_3CC_EECRH = 0xffffffff; // EERH - Disable high events
EDMA_3CC_ICRH = 0xffffffff; // ICRH - Clear high interrupts
EDMA_3CC_ECRH = 0xffffffff; // ICRH - Clear high events
EDMA_3CC_IECR = 0xffffffff; // IER - Disable low interrupts
EDMA_3CC_EECR = 0xffffffff; // EER - Disable low events
EDMA_3CC_ICR = 0xffffffff; // ICR - Clear low interrupts
EDMA_3CC_ECR = 0xffffffff; // ICRH - Clear low events
}
/* ------------------------------------------------------------------------ *
* *
* Enable_Instruction_Cache( ) *
* Enable I-Cache *
* *
* ------------------------------------------------------------------------ */
hotmenu Enable_Instruction_Cache( )
{
GEL_TextOut( "\Enable Instruction Cache.\n\n" );
CPSR = 0x400000d3; // Set to supervisor mode, disable IRQ/FIQ
REG_CP15_I_CACHE = 1; // Enable Instruction Cache
}
/* ------------------------------------------------------------------------ *
* *
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