test.v

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/****************************************************************************************
 *
 *   Company:  Micron Technology, Inc.
 *
 *   File Name:  TEST.V
 *
 ***************************************************************************************/

`timescale 1ns / 1ps

module test;

    parameter addr_bits =    13;
    parameter data_bits =     8;
    parameter full_clk  =     7.500;
    parameter half_clk  =     3.750;
    parameter quar_clk  =     1.875;
    parameter HiZ       =     8'bz;

    reg  [data_bits - 1 : 0] Dq;
    reg                      Dqs;
    reg  [addr_bits - 1 : 0] Addr;
    reg              [1 : 0] Ba;
    reg                      Clk;
    reg                      Clk_n;
    reg                      Cke;
    reg                      Cs_n;
    reg                      Ras_n;
    reg                      Cas_n;
    reg                      We_n;
    reg                      Dm;

    wire [data_bits - 1 : 0] DQ  = Dq;
    wire                     DQS = Dqs;

    mt46v64m8 sdramddr (DQ, DQS, Addr, Ba, Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Dm);

    always begin
        #half_clk;
        Clk_n = ~Clk_n;
        Clk   = ~Clk_n;
    end

    initial begin
        Clk   =  1'b0;
        Clk_n =  1'b1;
        Cke   =  1'b0;
        Cs_n  =  1'b0;
        Ras_n =  1'b1;
        Cas_n =  1'b1;
        We_n  =  1'b1;
        Dm    =  1'b0;
        Addr  = 13'b0;
        Ba    =  2'b0;
        Dq    =  HiZ;
        Dqs   =  1'bz;
        // Verilog-XL Wave-form display
        //$shm_open ("waves.shm");
        //$shm_probe(test, "AC");
    end

// 200 us Power-up sequence
task power_up;
    begin
        Cke   =  1'b0;
        Cs_n  =  1'bx;
        Ras_n =  1'bx;
        Cas_n =  1'bx;
        We_n  =  1'bx;
        Dm    =  1'bx;
        Ba    =  2'bx;
        Addr  = 13'bx;
        Dq    =  HiZ;
        Dqs   =  1'bz;
        #200000;
        Cke   =  1'b1;
        Cs_n  =  1'b0;
        Ras_n =  1'b1;
        Cas_n =  1'b1;
        We_n  =  1'b1;
        Dm    =  1'b0;
    end
endtask


task active;
    input             [1 : 0] ba;
    input [addr_bits - 1 : 0] addr;
    input [data_bits - 1 : 0] dq;
    input                     dqs;
    input                     dm;
    begin
        Cke   = 1'b1;
        Cs_n  = 1'b0;
        Ras_n = 1'b0;
        Cas_n = 1'b1;
        We_n  = 1'b1;
        Dm    =   dm;
        Ba    =   ba;
        Addr  = addr;
        Dq    =   dq;
        Dqs   =  dqs;
        #full_clk;
    end
endtask

task auto_refresh;
    begin
        Cke   =  1'b1;
        Cs_n  =  1'b0;
        Ras_n =  1'b0;
        Cas_n =  1'b0;
        We_n  =  1'b1;
        Dm    =  1'b0;
        //Ba    =  2'b0;
        //Addr  = 12'b0;
        Dq    =   HiZ;
        Dqs   =  1'bz;
        #full_clk;
    end
endtask

task burst_term;
    input                     dm;
    begin
        Cke   =  1'b1;
        Cs_n  =  1'b0;
        Ras_n =  1'b1;
        Cas_n =  1'b1;
        We_n  =  1'b0;
        Dm    =    dm;
        //Ba    =  2'b0;
        //Addr  = 12'b0;
        Dq    =   HiZ;
        Dqs   =  1'bz;
        #full_clk;
    end
endtask

task precharge;
    input             [1 : 0] ba;
    input [addr_bits - 1 : 0] addr;
    begin
        Cke   = 1'b1;
        Cs_n  = 1'b0;
        Ras_n = 1'b0;
        Cas_n = 1'b1;
        We_n  = 1'b0;
        Dm    = 1'b0;
        Ba    =   ba;
        Addr  = addr;
        Dq    =  HiZ;
        Dqs   = 1'bz;
        #full_clk;
    end
endtask


task load_mode_reg;
    input             [1 : 0] ba;
    input [addr_bits - 1 : 0] addr;
    begin
        Cke   = 1'b1;
        Cs_n  = 1'b0;
        Ras_n = 1'b0;
        Cas_n = 1'b0;
        We_n  = 1'b0;
        Dm    = 1'b0;
        Ba    =   ba;
        Addr  = addr;
        Dq    =  HiZ;
        Dqs   = 1'bz;
        #full_clk;
    end
endtask

task nop;
    input [data_bits - 1 : 0] dq;
    input                     dqs;
    input                     dm;
    begin
        Cke   =  1'b1;
        Cs_n  =  1'b0;
        Ras_n =  1'b1;
        Cas_n =  1'b1;
        We_n  =  1'b1;
        Dm    =    dm;
        //Ba    =  2'b0;
        //Addr  = 12'b0;
        Dq    =    dq;
        Dqs   =   dqs;
        #full_clk;
    end
endtask

task read;
    input             [1 : 0] ba;
    input [addr_bits - 1 : 0] addr;
    begin
        Cke   = 1'b1;
        Cs_n  = 1'b0;
        Ras_n = 1'b1;
        Cas_n = 1'b0;
        We_n  = 1'b1;
        Dm    = 1'b0;
        Ba    =   ba;
        Addr  = addr;
        Dq    =  HiZ;
        Dqs   = 1'bz;
        #full_clk;
    end
endtask

// Write Burst Length = 2
task write_2;
    input             [1 : 0] ba;       // Bank
    input [addr_bits - 1 : 0] addr;     // Column
    input [data_bits - 1 : 0] dq0;      // First Data
    input [data_bits - 1 : 0] dq1;      // Last Data
    begin
                    Cke   = 1'b1;
                    Cs_n  = 1'b0;
                    Ras_n = 1'b1;
                    Cas_n = 1'b0;
                    We_n  = 1'b0;
                    Dm    = 1'b0;
                    Ba    =   ba;
                    Addr  = addr;
                    Dq    =  HiZ;
                    Dqs   = 1'bz;
        #half_clk;  Dqs   = 1'b0;
        #half_clk;  Cas_n = 1'b1;
                    We_n  = 1'b1;
        #quar_clk;  Dq    = dq0;
        #quar_clk;  Dqs   = 1'b1;
        #quar_clk;  Dq    = dq1;
        #quar_clk;  Dqs   = 1'b0;
        #quar_clk;  Dq    = HiZ;
        #quar_clk;  Dqs   = 1'bz;
        #half_clk;
        #full_clk;
    end
endtask

// Write Burst Length = 4
task write_4;
    input             [1 : 0] ba;       // Bank
    input [addr_bits - 1 : 0] addr;     // Column
    input [data_bits - 1 : 0] dq0;      // First Data
    input [data_bits - 1 : 0] dq1;