mt46v64m8.v

来自「If you have not registered, Please [regi」· Verilog 代码 · 共 30 行

/****************************************************************************************
*
*    File Name:  MT46V64M8.V  
*      Version:  3.1
*         Date:  March 19th, 2002
*        Model:  BUS Functional
*    Simulator:  Aldec, ModemSim, NCDesktop
*
* Dependencies:  None
*
*       Author:  Son P. Huynh
*        Email:  [e-mail]
*        Phone:  [phone]
*      Company:  Micron Technology, Inc.
*  Part Number:  MT46V64M8 (16Meg x 8 x 4 Banks)
*
*  Description:  Micron 512Mb SDRAM DDR (Double Data Rate)
*
*   Limitation:  - Doesn't check for 8K-cycle refresh
*
*         Note:  - Set simulator resolution to "ps" accuracy
*                - Set Debug = 0 to disable $display messages
*                - Model assume Clk and Clk# crossing at both edge
*
*   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
*                WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY 
*                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
*                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
*
*                Copyright