testbench.v.bak

ARM10 INSTALALTION GUIDE

module test_arm();

reg GCLK;
reg nRESET;
reg BIGEND;
reg [1:0] CHSD, CHSE;
wire LATECANCEL, PASS;
wire [4:0] InM;


arm7 My_Arm7( .nOPC(), .nCPI(), .CPA(), .CPB(), .sysclk(GCLK), .nRESET(nRESET), .nFIQ(), .nIRQ(), .ABORT(), .nMREQ(), .nRW(), .MAS(), .nWAIT(), .A_MAR(), .D());


initial
begin
	nRESET=1'b1;
	BIGEND=1'b0;
	GCLK=1'b0;
	CHSE = 2'b10;
	CHSD = 2'b10;
	$readmemh("testarm.vhx", arm10.mem);
	#11.5;
	nRESET=1'b0;
	#10 nRESET=1'b1;
end

always #50 GCLK = ~GCLK;

endmodule