_primary.vhd

来自「ARM10 INSTALALTION GUIDE」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity cla6 is
    port(
        cout            : out    vl_logic_vector(5 downto 0);
        c_overflow      : out    vl_logic;
        p               : in     vl_logic_vector(5 downto 0);
        g               : in     vl_logic_vector(5 downto 0);
        cin             : in     vl_logic
    );
end cla6;