_primary.vhd

来自「ARM10 INSTALALTION GUIDE」· VHDL 代码 · 共 29 行

library verilog;
use verilog.vl_types.all;
entity memory_coupler is
    port(
        A               : in     vl_logic_vector(31 downto 0);
        mem_A           : out    vl_logic_vector(31 downto 0);
        mem_D           : inout  vl_logic_vector(31 downto 0);
        mem_nRAS        : out    vl_logic;
        mem_nCAS        : out    vl_logic;
        mem_nRW         : out    vl_logic;
        mem_SEQ         : out    vl_logic;
        mem_nCS         : out    vl_logic;
        mem_MCLK        : out    vl_logic;
        mem_BYTE        : out    vl_logic;
        st_busy         : out    vl_logic;
        ld_busy         : out    vl_logic;
        write_buffer_is_byte: in     vl_logic;
        write_buffer_D  : in     vl_logic_vector(31 downto 0);
        write_buffer_A  : in     vl_logic_vector(31 downto 0);
        Store_Trigger   : in     vl_logic;
        Load_Trigger    : in     vl_logic;
        load_from_mem_req: out    vl_logic;
        load_from_mem_data: out    vl_logic_vector(31 downto 0);
        load_from_mem_offset: out    vl_logic_vector(1 downto 0);
        clk             : in     vl_logic;
        reset           : in     vl_logic
    );
end memory_coupler;