_primary.vhd

来自「ARM10 INSTALALTION GUIDE」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity Booth_multiplier is
    port(
        Multiplier_enable: in     vl_logic;
        Multiplier_A    : in     vl_logic_vector(31 downto 0);
        Multiplier_B    : in     vl_logic_vector(31 downto 0);
        Multiplier_Result: out    vl_logic_vector(31 downto 0);
        Multiplier_ready: out    vl_logic;
        sysclk          : in     vl_logic
    );
end Booth_multiplier;