_primary.vhd

来自「ARM10 INSTALALTION GUIDE」· VHDL 代码 · 共 25 行

library verilog;
use verilog.vl_types.all;
entity CPU_coupler is
    port(
        D               : inout  vl_logic_vector(31 downto 0);
        A               : in     vl_logic_vector(31 downto 0);
        nMREQ           : in     vl_logic;
        nRW             : in     vl_logic;
        MAS             : in     vl_logic_vector(1 downto 0);
        nWAIT           : out    vl_logic;
        sysclk          : in     vl_logic;
        reset           : in     vl_logic;
        Store_Trigger   : out    vl_logic;
        Load_Trigger    : out    vl_logic;
        write_buffer_data: out    vl_logic_vector(31 downto 0);
        write_buffer_addr: out    vl_logic_vector(31 downto 0);
        write_buffer_is_byte: out    vl_logic;
        st_busy         : in     vl_logic;
        ld_busy         : in     vl_logic;
        load_from_mem_req: in     vl_logic;
        load_from_mem_data: in     vl_logic_vector(31 downto 0);
        load_from_mem_offset: in     vl_logic_vector(1 downto 0)
    );
end CPU_coupler;