voptkrf6j3

ARM10 INSTALALTION GUIDE

library verilog;
use verilog.vl_types.all;
entity wd_reg is
    port(
        WD_Bus_Write    : in     vl_logic_vector(31 downto 0);
        WD_DBE          : in     vl_logic;
        WD_Load         : in     vl_logic;
        WD_DOUT         : out    vl_logic_vector(31 downto 0);
        sysclk          : in     vl_logic
    );
end wd_reg;