voptga3n1n

ARM10 INSTALALTION GUIDE

library verilog;
use verilog.vl_types.all;
entity sign_extend is
    port(
        IR2110          : in     vl_logic_vector(11 downto 0);
        IR2_MUL70       : in     vl_logic_vector(7 downto 0);
        IR270           : in     vl_logic_vector(7 downto 0);
        IR2230          : in     vl_logic_vector(23 downto 0);
        SZE_SEL         : in     vl_logic_vector(1 downto 0);
        SZE_CTRL        : in     vl_logic;
        BS_INPUT_SEL_EXT: out    vl_logic_vector(31 downto 0)
    );
end sign_extend;