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来自「ARM10 INSTALALTION GUIDE」· 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity addr_reg is
    port(
        AR_Bus_Alu      : in     vl_logic_vector(31 downto 0);
        AR_Bus_PC       : in     vl_logic_vector(31 downto 0);
        AR_Bus_PC_4     : in     vl_logic_vector(31 downto 0);
        AR_Bus_Sel      : in     vl_logic_vector(1 downto 0);
        AR_Output_Bus   : out    vl_logic_vector(31 downto 0);
        sysclk          : in     vl_logic
    );
end addr_reg;