📄 vopt29smy5
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library verilog;use verilog.vl_types.all;entity armcontroller is port( A_Addr_Sel : out vl_logic_vector(1 downto 0); B_Addr_Sel : out vl_logic; RF_Addr_Write_Sel: out vl_logic_vector(2 downto 0); RF_Bus_Write_Sel: out vl_logic_vector(2 downto 0); RF_PC_Write_Sel : out vl_logic_vector(3 downto 0); RF_Load_Write : out vl_logic; RF_Load_Flags : out vl_logic; RF_PSR_R_Sel : out vl_logic; RF_PSR_W_Sel : out vl_logic; RF_PSR_Read : in vl_logic_vector(31 downto 0); SC_Type : out vl_logic_vector(4 downto 0); SC_Source : out vl_logic_vector(3 downto 0); SZE_Sel : out vl_logic_vector(1 downto 0); SZE_Ctrl : out vl_logic; SAM_Ctrl : out vl_logic_vector(1 downto 0); BS_Input_Sel : out vl_logic; BS_Enable : out vl_logic; BS_Cin : out vl_logic; AR_Bus_ALU_Sel : out vl_logic_vector(1 downto 0); AR_Bus_Sel : out vl_logic_vector(1 downto 0); WD_DBE : out vl_logic; WD_Load : out vl_logic; nOPC : out vl_logic; nCPI : out vl_logic; CPA : in vl_logic; CPB : in vl_logic; nMREQ : out vl_logic; nRW : out vl_logic; MAS : out vl_logic_vector(1 downto 0); nWAIT : in vl_logic; Alu_A_Sel : out vl_logic_vector(1 downto 0); Alu_Cntrl : out vl_logic_vector(4 downto 0); Multiplier_Enable: out vl_logic; Multiplier_Ready: in vl_logic; ir2_bus : in vl_logic_vector(31 downto 0); ir2_mult_bus : in vl_logic_vector(31 downto 0); ir1_zero : out vl_logic; ir2_zero : out vl_logic; ld_ir2_mult : out vl_logic; nSTALL : out vl_logic; BBUS_Src : out vl_logic; sysclk : in vl_logic; nRESET : in vl_logic; ABORT : in vl_logic; nFIQ : in vl_logic; nIRQ : in vl_logic; ALU_Hold_Enable : out vl_logic; ALU_Hold_Sel : out vl_logic; Link_Sel : out vl_logic );end armcontroller;
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