voptazehw1

ARM10 INSTALALTION GUIDE

library verilog;
use verilog.vl_types.all;
entity shift_maker is
    port(
        ir2             : in     vl_logic_vector(31 downto 0);
        Reg_value       : in     vl_logic_vector(31 downto 0);
        SAM_Ctrl        : in     vl_logic_vector(1 downto 0);
        BS_Shift_Amt    : out    vl_logic_vector(4 downto 0);
        BS_Shift_Type   : out    vl_logic_vector(1 downto 0)
    );
end shift_maker;