ad.map.rpt

MAX125 AD 转换及转换后的数据读取

; 74373:inst9|17                                ;    ;
; 74373:inst9|18                                ;    ;
; 74373:inst9|19                                ;    ;
; 74373:inst7|12                                ;    ;
; Number of user-specified and inferred latches ; 42 ;
+-----------------------------------------------+----+


+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                  ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |AD                        ; 75         ; 141  ; |AD                 ;
;    |74373:inst5|           ; 8          ; 0    ; |AD|74373:inst5     ;
;    |74373:inst6|           ; 8          ; 0    ; |AD|74373:inst6     ;
;    |74373:inst7|           ; 8          ; 0    ; |AD|74373:inst7     ;
;    |74373:inst8|           ; 8          ; 0    ; |AD|74373:inst8     ;
;    |74373:inst9|           ; 8          ; 0    ; |AD|74373:inst9     ;
+----------------------------+------------+------+---------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/Users/GAO/Desktop/仿真全/AD/AD.map.eqn.


+---------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                        ;
+----------------------------------+-----------------+----------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path                             ;
+----------------------------------+-----------------+----------------------------------------------------------+
; AD.bdf                           ; yes             ; C:/Users/GAO/Desktop/仿真全/AD/AD.bdf                    ;
; 16dmux.bdf                       ; yes             ; c:/altera/quartus42/libraries/others/maxplus2/16dmux.bdf ;
; 74373.bdf                        ; yes             ; c:/altera/quartus42/libraries/others/maxplus2/74373.bdf  ;
+----------------------------------+-----------------+----------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 75                   ;
; Total registers      ; 0                    ;
; I/O pins             ; 141                  ;
; Shareable expanders  ; 19                   ;
; Parallel expanders   ; 5                    ;
; Maximum fan-out node ; A15                  ;
; Maximum fan-out      ; 86                   ;
; Total fan-out        ; 894                  ;
; Average fan-out      ; 3.80                 ;
+----------------------+----------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Mon Apr 27 14:14:57 2009
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off AD -c AD
Info: Found 1 design units, including 1 entities, in source file AD.bdf
    Info: Found entity 1: AD
Warning: Pin "MR" is missing source
Warning: Pin "RESET_N" not connected
Warning: Pin "WDO" not connected
Warning: Primitive "CARRY" of instance "inst314" not used
Warning: Primitive "CARRY" of instance "inst315" not used
Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/quartus42/libraries/others/maxplus2/16dmux.bdf
    Info: Found entity 1: 16dmux
Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/quartus42/libraries/others/maxplus2/74373.bdf
    Info: Found entity 1: 74373
Info: Ignored 124 buffer(s)
    Info: Ignored 124 CARRY buffer(s)
Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN
    Warning: Converting TRI node "inst282" that feeds logic to an OR gate
    Warning: Converting TRI node "inst284" that feeds logic to an OR gate
    Warning: Converting TRI node "inst286" that feeds logic to an OR gate
    Warning: Converting TRI node "inst288" that feeds logic to an OR gate
    Warning: Converting TRI node "inst274" that feeds logic to an OR gate
    Warning: Converting TRI node "inst276" that feeds logic to an OR gate
    Warning: Converting TRI node "inst278" that feeds logic to an OR gate
    Warning: Converting TRI node "inst280" that feeds logic to an OR gate
    Warning: Converting TRI node "IN~19" that feeds logic to an OR gate
    Warning: Converting TRI node "IN~32" that feeds logic to an OR gate
    Warning: Converting TRI node "IN~45" that feeds logic to an OR gate
    Warning: Converting TRI node "IN~57" that feeds logic to an OR gate
    Warning: Converting TRI node "IN~70" that feeds logic to an OR gate
    Warning: Converting TRI node "IN~83" that feeds logic to an OR gate
    Warning: Converting TRI node "IN~96" that feeds logic to an OR gate
    Warning: Converting TRI node "IN~108" that feeds logic to an OR gate
Warning: TRI or OPNDRN buffers permanently enabled
    Warning: Node "74373:inst5|67"
    Warning: Node "74373:inst5|68"
    Warning: Node "74373:inst5|69"
    Warning: Node "74373:inst5|70"
    Warning: Node "74373:inst5|71"
    Warning: Node "74373:inst5|72"
    Warning: Node "74373:inst5|73"
    Warning: Node "74373:inst5|74"
    Warning: Node "74373:inst6|67"
    Warning: Node "74373:inst6|68"
    Warning: Node "74373:inst6|69"
    Warning: Node "74373:inst6|70"
    Warning: Node "74373:inst6|71"
    Warning: Node "74373:inst6|72"
    Warning: Node "74373:inst6|73"
    Warning: Node "74373:inst6|74"
    Warning: Node "74373:inst7|68"
    Warning: Node "74373:inst7|69"
    Warning: Node "74373:inst7|70"
    Warning: Node "74373:inst7|71"
    Warning: Node "74373:inst7|72"
    Warning: Node "74373:inst7|73"
    Warning: Node "74373:inst7|74"
    Warning: Node "74373:inst8|67"
    Warning: Node "74373:inst8|68"
    Warning: Node "74373:inst8|69"
    Warning: Node "74373:inst8|70"
    Warning: Node "74373:inst8|71"
    Warning: Node "74373:inst8|72"
    Warning: Node "74373:inst8|73"
    Warning: Node "74373:inst8|74"
    Warning: Node "74373:inst9|67"
    Warning: Node "74373:inst9|68"
    Warning: Node "74373:inst9|69"
    Warning: Node "74373:inst9|70"
    Warning: Node "74373:inst9|71"
    Warning: Node "74373:inst9|72"
    Warning: Node "74373:inst9|73"
    Warning: Node "74373:inst9|74"
    Warning: Node "74373:inst7|67"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "LP_RESET_N" stuck at VCC
    Warning: Pin "MR" stuck at GND
Warning: Design contains 2 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "RESET_N"
    Warning: No output dependent on input pin "WDO"
Info: Implemented 235 device resources after synthesis - the final resource count might be different
    Info: Implemented 78 input pins
    Info: Implemented 51 output pins
    Info: Implemented 12 bidirectional pins
    Info: Implemented 75 macrocells
    Info: Implemented 19 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 69 warnings
    Info: Processing ended: Mon Apr 27 14:15:00 2009
    Info: Elapsed time: 00:00:03