mpa_layer2mc.s

samsung 9908DVD源代码,

/*
 *  mpa_layer2mc.s
 *
 *  MPEG/audio multichannel decoder.
 *	Copyright (C) 2003 Optical Player P/J, Samsung Electronics.
 *
 */
 
.include	"mpa.h"

.if( _DECODER_TYPE != MPEG_1_AUDIO )

.extern		MPG_II_decode_sample
.extern		MPG_II_denormalize_sample

.secFILE_mpa_layer2mc

				
/********************************************************************

 Function:		MC_layer_II_decode

 Description:	

********************************************************************/
MC_layer_II_decode::
				push		a10, a14

				

;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;
;::                                                                ::;
;::              Decode composite status information               ::;
;::                                                                ::;
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;
;				index registers 
;				@bank0
;						d1		d0		s1		s0
;				---------------------------------------
;				sd0: 	 x		 1		 x		 x
;				sd1: 	 x		 1		 x		 x
;				sd2: 	 x		 1		 x		 x
; 
MC_composite_status_info
				ebk			#0000b
				er			xsd
				esd0		d0, #1
				esd1		d0, #1
				esd2		d0, #1
				
				eld			a, #1
				jsr			getbits
				eld			rpd1.tc_sbgr_select, d
				ecld		r0, d
				eld			a, #1
				jsr			getbits
				eld			rpd1.dyn_cross_on, d
				ecld		r1, d
				eld			a, #1
				jsr			getbits
				eld			rpd1.mc_prediction_on, d
				ecld		r2, d

transmission_channel_info
; Whether the tc_allocation is valid for all subbands
				eld			rp0, #tc_alloc
				eld			a, rpd1.tc_alloc_bits
				ecld		r4, a
				cmp			eq, r0, #TRUE
				brtd		%f1
				ld			r7, #GRANULES-1
				eld			c, #0
				eld			rpd1.tc_allocation, c
%0				ecld		a, r4
				jsr			getbits
				bnzd		r7, %b0
				eld			@rp0+d0, d
				bra			dynamic_crosstalk_info
%1				ecld		a, r4
				jsr			getbits
				eld			rpd1.tc_allocation, d
				bnzd		r7, $
				eld			@rp0+d0, d				
				
dynamic_crosstalk_info
; Whether dynamic crosstalk is used
				eld			rp1, #dyn_cross_mode				
				cmp			eq, r1, #TRUE
				brtd		%2
				ld			r7, #GRANULES-1				
				eld			c, #0
				eld			rpd1.dyn_cross_LR, c				
				bnzd		r7, $
				eld			@rp1+d0, c
				bra			mc_prediction_info
%2				eld			a, rpd0.surround
				ecld		r3, a
				eld			a, rpd1.dyn_cross_bits
				ecld		r4, a
				ld			r8, r4			; r8 used in bit_alloc at dyn_cross mode
				eld			rp2, #dyn_second_stereo
				eld			a, #1
				jsr			getbits
				eld			rpd1.dyn_cross_LR, d
%3				ecld		a, r4
				jsr			getbits
				eld			@rp1+d0, d
				cmp			eq, r3, #SECOND_STEREO
				brfd		%f33
				eld			a, #1
				jsr			getbits
%33				bnzd		r7, %b3
				eld			@rp2+d0, d
				
mc_prediction_info
; mc prediction mode is not supported.
;				cmp			eq, r2, #TRUE
;				brtd		end_of_mc_layer_II_decoding
;				mRETURN		(_ILLEGAL_MC_PRED_MODE)




;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;
;::                                                                ::;
;::                      Decode bit allocations                    ::;
;::                                                                ::;
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;
;				index registers 
;				@bank0
;						d1		d0		s1		s0
;				---------------------------------------
;				sd0: 	 x		 1		 x		 x
;				sd1: 	 x		 x		 0		 1
; 
MC_II_decode_bit_alloc
				eld			sd0, #0x0100
				eld			sd1, #0x0001

decode_lfe_bitalloc
				eld			a, rpd0.lfe
				ecp			a, #TRUE
				ebrad		ec1, %f1
				eld			d, #0
				eld			a, #4
				jsr			getbits
%1				eld			rpd1.lfe_allocation, d				

decode_mc_bitalloc
				eld			rp0, #bit_alloc+64
				eld			rp1, #nbal_table				

				eld			b, rpd0.center
				ecld		r0, b
				eld			c, rpd0.surround
				ecld		r1, c
				eld			a, rpd1.dyn_cross_on
				eld			b, rpd1.sblimit_mc
				eld			c, rpd1.mc_channel
				eld			d, rpd1.stereo
				ecld		r2, c
				eadd		c, d
				ecld		r7, b
				ecld		r6, c
				ecld		r5, d					; start ch
				ld			r11, r7					; mc_sblimit
				ld			r10, r6					; total channels
				ld			r12, r2					; mc_channel
				
				ecp			a, #TRUE
				ebrad		ec0, dynamic_crosstalk_mode_on
				ld			r6, r5
				ld			r7, #0
dynamic_crosstalk_mode_off
				cmp			ge, r0, #PHANTOM_CENTER
				brf			%f0
				cmp			ge, r7, #12
				brf			%f0
				cmp			eq, r6, #2
				brtd		mc_bitalloc_ch_loop_check
				eld			d, #0				
%0				eld			a, @rp1+s1
				jsr			getbits
mc_bitalloc_ch_loop_check
				inc			r6
				cmp			eq, r6, r10
				brfd		dynamic_crosstalk_mode_off
				eld			@rp0+d0, d
mc_bitalloc_sb_loop_check
				erps		rp1+s0
				inc			r7
				cmp			eq, r7, r11
				brfd		dynamic_crosstalk_mode_off
				ld			r6, r5
				bra			MC_II_decode_scfsi
				
dynamic_crosstalk_mode_on
				jsr			MC_II_dyncross_bitalloc
				



;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;
;::                                                                ::;
;::            Decode scalefactor selection information            ::;
;::                                                                ::;
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;
;				index registers 
;				@bank0
;						d1		d0		s1		s0
;				---------------------------------------
;				sd0: 	 x		 x		 x		 1
;				sd1: 	 x		 1		 x		 x
; 
MC_II_decode_scfsi
				er			xsd
				esd0		s0, #1
				esd1		d0, #1
				eld			rp0, #bit_alloc+64
				eld			rp1, #scfsi
				ld			r6, r11						; mc_sblimit
				ld			r4, r12						; mc_channel
				mul			uu, r6, r4					; sblimit x nmch
				dec			r6
				ld			r7, r6
%0				eld			a, @rp0+s0
				ecp			a, #0
				ebrad		ec0, %f1
				eld			d, #4						; default 4
				eld			a, #2
				jsr			getbits
%1				bnzd		r6, %b0
				eld			@rp1+d0, d



;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;
;::                                                                ::;
;::                 Decode prediction coefficients                 ::;
;::                                                                ::;
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;
MC_II_decode_pred_coef
; if((mc_channels > stereo) && (mc_prediction_on==1))
;				cmp			gt, r12, r5
;				brf			MC_II_decode_scalefactor
;				eld			a, rpd1.mc_prediction_on
;				ecp			a, #TRUE
;/** debug **/	ebra		ec0, $		; (mc prediction mode is not support)


				
				
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;
;::                                                                ::;
;::                      Decode scalefactors                       ::;
;::                                                                ::;
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;
;				index registers 
;				@bank0
;						d1		d0		s1		s0
;				---------------------------------------
;				sd0: 	 x		 x		 x		 1
;				sd1: 	 x		 x		 x		 1
;				sd2: 	 x		 1		 x		 x
; 
MC_II_decode_scalefactor
				er			xsd
				esd0		s0, #1
				esd1		s0, #1
				esd2		d0, #1
				eld			rp0, #bit_alloc+64
				eld			rp1, #scfsi
				eld			rp2, #scale_index+NCH*PARTS*SBLIMIT
				
decode_lfe_scalefactor
				eld			a, rpd0.lfe
				ecp			a, #TRUE
				ebra		ec1, decode_mc_scalefactor
				eld			a, rpd1.lfe_allocation
				ecp			a, #0
				ebra		ec0, decode_mc_scalefactor
				eld			a, #6
				jsr			getbits
				eld			rpd1.lfe_scalefactor, d

decode_mc_scalefactor
				eld			a, @rp0+s0						; bit_alloc[sb][ch]
				ecp			a, #0
				ebra		ec0, mc_default_scalefactor

				eld			a, #6
				jsr			getbits
				eld			@rp2+d0, d						; scale_index[sb][ch][0]
				
				eld			b, @rp1+s0						; scfsi[sb][ch]				
				ecp			b, #2
				ebrad		ec0, mc_scale_one
				ecld		r5, b
				ecp			b, #0
				ebra		ec0, mc_scale_all
				brad		mc_scale_1_3
				ecld		r4, d

mc_scale_one	brad		%f1
				eld			@rp2+d0, d 
				
mc_scale_all	eld			a, #6
				jsr			getbits
				eld			@rp2+d0, d 
mc_scale_1_3
mc_scale_1_2	eld			a, #6				
				jsr			getbits
				sr			r5
				brf			%f1
				sr			r5
				brf			%f0
				brad		%f1
				eld			@rp2+d0, d 	; scale_index[sb][ch][1] = scale_index[sb][ch][2]
%0				ecld		c, r4 		; scale_index[sb][ch][1] = scale_index[sb][ch][0]
				eld			@rp2+d0, c
%1				bnzd		r7, decode_mc_scalefactor
				eld			@rp2+d0, d 				 		; scale_index[sb][ch][2]
				bra			mc_error_check
				
mc_default_scalefactor
				eld			d, #63
				erps		rp1+s0
				eld			@rp2+d0, d
				brad		%b1
				eld			@rp2+d0, d				


;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;
;::                                                                ::;
;::                           MC CRC check                         ::;
;::                                                                ::;
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;
; mandatory CRC check
mc_error_check
				eld			a, rpd1.mandatory_crc_check
				ecp			a, #TRUE
				ebra		ec1, MC_II_decode_subband_sample
				jsr			MC_error_check
				eld			a, rpd0.mc_crc_val
				ecp			a, c
				ebra		ec0, MC_II_decode_subband_sample
.ifdef _DEBUG_
/** debug **/	bra			$
.endif

; If CRC error, clear bit_alloc buffer
				eld			b, rpd1.error_count
				eadd		b, #1
				eld			rpd1.error_count, b

				brad		end_of_mc_layer_II_decoding
				mRETURN		(_MC_CRC_ERROR)


				
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;
;::                                                                ::;
;::                      Decode mc samples                         ::;
;::                                                                ::;
;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::;
; fraction buffer structure
;	gr0 	ch2   0x20c0	:<---  96  --->:
;			ch3   0x2120	:<---  96  --->:
;			ch4   0x2180	:<---  96  --->:
; 
;				index registers 
;				@bank0
;						d1		d0		s1		s0
;				---------------------------------------
;				sd0:   +32		 1	   -96     -95
;				sd1: 	 x		 x		 x		 1
;				sd2: 	 x		 x		 0		 x
; 				
;				@bank1 (dyn_cross_on == 1)
;						d1		d0		s1		s0
;				---------------------------------------
;				sd0: 	 x		 x		 x		16
;				sd1: 	 x		 x		 x		 x
;				sd2: 	 x		 1		 x		 x
;				sd3:   -96		 x		32		17
; 
MC_II_decode_subband_sample
				es			psh1
				es			usm			; used in mDEQUANT_SAMPLE
				es			op
				es			opm

				ebk			#1111b
				er			xsd
				eld			sd0, #0x0000
				eld			sd3, #0x0001
				es			xsd
				eld			sd0, #0x0001
				eld			sd3, #0xa021
				eld			sd1, #0x0000
				eld			sd2, #0x0100
				
				ebk			#0000b
				er			xsd
				eld			sd0, #0x0101
				es			xsd
				eld			sd0, #0x20aa
				eld			sd1, #0x0001
				eld			sd2, #0x0000

; configuration for dynamic crosstalk mode
; bank 1 RAM pointers used
				eld			a, rpd1.dyn_cross_on
				ecld		r1, a
				ld			r9, r1
				eld			a, rpd1.dyn_cross_bits
				ebk			#0111b
				eld			rp1, #tc_table			; dyn_cross_bits = 4
				ecp			a, #4
				ebra		ec0, %f1
				eld			rp1, #tc_table+16*3		; dyn_cross_bits = 3
				ecp			a, #3
				ebra		ec0, %f1
				eld			rp1, #tc_table+16*5		; dyn_cross_bits = 1
				ecp			a, #1
				ebra		ec0, %f1

				eld			a, rpd0.surround
				eld			b, rpd0.center
				ecp			a, #SECOND_STEREO
				ebra		ec1, %f1
				ecp			b, #CENTER_NONE
				ebra		ec1, %f1			
				eld			rp1, #tc_table+16*6		; second stereo, no center