📄 geq.s
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.include "config_geq.h"
.extern BANK1_48k, BANK1_44k1, BANK1_32k, ROCK_MODE
.extern _s0_base_ptr_geq, _s1_base_ptr_geq, LDelayBuf1_geq, RDelayBuf1_geq
//.extern _load_geq_coeff
.extern LDelayBuf9_geq, RDelayBuf9_geq
eq_section section code
eq_section
_Equalizer::
push a14
push a8, a9
push r0, r1
push r2, r3
push r4, r5
push r6, r7
eld a, #0
eld msr0, a
eld msr1, a
eld msr2, a
es psh1
es opm
es op
ldw r0, @[a10+CodecStartFlag]
cmp eq, r0, #0
brf %f1
jsr _load_geq_coeff
jsr _init_geq
ld r1, #1
ldw @[a10+CodecStartFlag], r1
bra end_eq
%1:
ld a8, #ADM_BASE
ldw r0, @[a8+rCONFIG0]
and r0, #0xf0
ldb r7, @[a10+PCMResolution]
cmp eq, r7, #16
brf %f50
or r0, #SBF0_R16msb+SBF1_W16msb
bra %f51
%50:
or r0, #0x0000
%51:
ldw @[a8+rCONFIG0], r0
ldw r3, @[a10+InputBufferOffset]
ldw r4, @[a10+InputBufferOffset+2]
ldw @[a8+rSB0OFF_H], r3
ldw @[a8+rSB0OFF_L], r4
ldw r3, @[a10+OutputBufferOffset]
ldw r4, @[a10+OutputBufferOffset+2]
ldw @[a8+rSB1OFF_H], r3
ldw @[a8+rSB1OFF_L], r4
ld r0, #SBF0_FILL
ldw @[a8+rSBFCON], r0
esd0 s0, #1
esd0 s1, #-4
esd0 d0, #1
esd1 s0, #0
esd2 d0, #0
esd2 s0, #1
esd3 s0, #1
esd3 s1, #-1
eld rp1, #0x7ffe
eld rp2, #0x7fff
ldw r2, @[a10+NumberOfSample]
/* Mode setting */
ldw r1, @[a10+SamplingRate+2]
cmp eq, r1, #48000
brf %f1
eld b, #BANK1_48k
bra %f10
%1:
cmp eq, r1, #44100
brf %f2
eld b, #BANK1_44k1
bra %f10
%2:
eld b, #BANK1_32k
%10:
ldw a8, @[a10+pParameter]
ldb r1, @[a8+EQ_Mode] ;EQ mode
cmp eq, r1, #Normal
brt bypass_eq
eld d, #0
eld si, #0
eld d, #ROCK_MODE
sub r1, #1
ld r0, #10
mul uu, r0, r1
ecld si, r0
eadd d, si
loop:
/* Left */
eld rp0, #LDelayBuf1_geq ;delay buffer
eld rp3, b ;coeff table
eld c, @rp1+s0
esra c
eld x1, c
ld r6, #9-1
eld ma1, #0
/*********************** BANK 1 ~ BANK 9 *****************************/
/* y(n) = b0 x(n) + b1 x(n-1) + b2 x(n-2) - a2 y(n-2) - a1 y(n-1) : 鉴辑 林狼 */
%1:
eld y0, @rp3+s0
emul x1y0, x0, @rp0+s0, y0, @rp3+s0
eld c, x0
emld ma0, x0y0, x0, @rp0+s0, y0, @rp3+s0
emad ma0, x0y0, x0, @rp0+s0, y0, @rp3+s0
emad ma0, x0y0, x0, @rp0+s0, y0, @rp3+s0
emsb ma0, x0y0
esub ma0, p
esla ma0
erpn rp0, #-4
eld @rp0+d0, x1 //x(n-1)
eld @rp0+d0, c //x(n-2)
eld @rp0+d0, x0 //y(n-2)
eld @rp0+d0, ma0 //y(n-1)
bnzd r6, %b1
erps rp3+s0
/************************************************************************/
eld rp0, #LDelayBuf9_geq
erpn rp0, #3
eld rp3, d ;gain table
erpn rp3, #9
ld r6, #4-1
%2:
eld a, x1
eld x0, @rp0+s1, y0, @rp3+s1
esub a, x0
eld x1, a
emul x1y0
eadd ma1, p
eld a, x0
eld x1, @rp0+s1, y0, @rp3+s1
esub a, x1
eld x0, a
emul x0y0
eadd ma1, p
bnzd r6, %b2
nop
eld a, x1
eld x0, @rp0+s1, y0, @rp3+s1
esub a, x0
eld x1, a
emul x1y0
eadd ma1, p
eld y0, @rp3+s1
emul x0y0
eadd ma1, p
esla ma1
esla ma1
esla ma1
/************************************************************************/
.ifdef OUTPUT_2CH
eld @rp2+d0, ma1
.endif
.ifdef OUTPUT_6CH
eld @rp2+d0, ma1
eld sr, @rp1+s0
eld @rp2+d0, sr
eld sr, @rp1+s0
eld @rp2+d0, sr
.endif
.ifdef OUTPUT_8CH
eld @rp2+d0, ma1
eld sr, @rp1+s0
eld @rp2+d0, sr
eld sr, @rp1+s0
eld @rp2+d0, sr
eld sr, @rp1+s0
eld @rp2+d0, sr
.endif
/* Right */
eld rp0, #RDelayBuf1_geq ;delay buffer
eld rp3, b ;coeff table
eld c, @rp1+s0
esra c
eld x1, c
ld r6, #9-1
eld ma1, #0
/*********************** BANK 1 ~ BANK 10 *****************************/
/* y(n) = b0 x(n) + b1 x(n-1) + b2 x(n-2) - a2 y(n-2) - a1 y(n-1) : 鉴辑 林狼 */
%1:
eld y0, @rp3+s0
emul x1y0, x0, @rp0+s0, y0, @rp3+s0
eld c, x0
emld ma0, x0y0, x0, @rp0+s0, y0, @rp3+s0
emad ma0, x0y0, x0, @rp0+s0, y0, @rp3+s0
emad ma0, x0y0, x0, @rp0+s0, y0, @rp3+s0
emsb ma0, x0y0
esub ma0, p
esla ma0
erpn rp0, #-4
eld @rp0+d0, x1 //x(n-1)
eld @rp0+d0, c //x(n-2)
eld @rp0+d0, x0 //y(n-2)
eld @rp0+d0, ma0 //y(n-1)
bnzd r6, %b1
erps rp3+s0
/************************************************************************/
eld rp0, #RDelayBuf9_geq
erpn rp0, #3
eld rp3, d ;gain table
erpn rp3, #9
ld r6, #4-1
%2:
eld a, x1
eld x0, @rp0+s1, y0, @rp3+s1
esub a, x0
eld x1, a
emul x1y0
eadd ma1, p
eld a, x0
eld x1, @rp0+s1, y0, @rp3+s1
esub a, x1
eld x0, a
emul x0y0
eadd ma1, p
bnzd r6, %b2
nop
eld a, x1
eld x0, @rp0+s1, y0, @rp3+s1
esub a, x0
eld x1, a
emul x1y0
eadd ma1, p
eld y0, @rp3+s1
emul x0y0
eadd ma1, p
esla ma1
esla ma1
esla ma1
/************************************************************************/
.ifdef OUTPUT_2CH
eld @rp2+d0, ma1
.endif
.ifdef OUTPUT_6CH
eld @rp2+d0, ma1
eld sr, @rp1+s0
eld @rp2+d0, sr
eld sr, @rp1+s0
eld @rp2+d0, sr
.endif
.ifdef OUTPUT_8CH
eld @rp2+d0, ma1
eld sr, @rp1+s0
eld @rp2+d0, sr
eld sr, @rp1+s0
eld @rp2+d0, sr
eld sr, @rp1+s0
eld @rp2+d0, sr
.endif
dt r2
brf loop
end_eq:
ld a8, #ADM_BASE
ld r0, #SBF1_FLUSH
ldw @[a8+rSBFCON], r0
pop r7, r6
pop r5, r4
pop r3, r2
pop r1, r0
pop a9, a8
pop a14
ret
bypass_eq:
.ifdef OUTPUT_2CH
eld b, @rp1+s0
eld @rp2+d0, b
eld b, @rp1+s0
eld @rp2+d0, b
.endif
.ifdef OUTPUT_6CH
eld b, @rp1+s0
eld @rp2+d0, b
eld b, @rp1+s0
eld @rp2+d0, b
eld b, @rp1+s0
eld @rp2+d0, b
eld b, @rp1+s0
eld @rp2+d0, b
eld b, @rp1+s0
eld @rp2+d0, b
eld b, @rp1+s0
eld @rp2+d0, b
.endif
.ifdef OUTPUT_8CH
eld b, @rp1+s0
eld @rp2+d0, b
eld b, @rp1+s0
eld @rp2+d0, b
eld b, @rp1+s0
eld @rp2+d0, b
eld b, @rp1+s0
eld @rp2+d0, b
eld b, @rp1+s0
eld @rp2+d0, b
eld b, @rp1+s0
eld @rp2+d0, b
eld b, @rp1+s0
eld @rp2+d0, b
eld b, @rp1+s0
eld @rp2+d0, b
.endif
dt r2
brf bypass_eq
bra end_eq
_init_geq:
/* clear buffer */
esd1 d0, #1
eld a, #0
ld r6, #4*9-1
eld rp1, #LDelayBuf1_geq
bnzd r6, $
eld @rp1+d0, a
ld r6, #4*9-1
eld rp1, #RDelayBuf1_geq
bnzd r6, $
eld @rp1+d0, a
ret
.extern |GEQ_MEM$$geq_coeff$$LOAD|
.extern |GEQ_MEM$$geq_coeff$$SIZE|
.extern |GEQ_MEM$$geq_coeff$$START|
_load_geq_coeff::
push R4, R6
push A11, A12
push A13
ld R6, #|GEQ_MEM$$geq_coeff$$SIZE|
sub R6, #1
ld A11, #|GEQ_MEM$$geq_coeff$$LOAD|
ld A12, #0x220000+(StartAddress_Ymem_Mac-0x8000)*2
ld A13, #0x220000+(StartAddress_Ymem_Mac-0x8000)*2 + 0x10000
ldc R4, @A11
%1
push R4
srb R4
ldb @[A13+1], R4
pop R4
and R4, #0x00ff
ldb @[A12+0], R4
add A11, #2
add A13, #2
ldc R4, @A11
push R4
srb R4
ldb @[A12+1], R4
pop R4
and R4, #0x00ff
ldb @[A13+1], R4
add A11, #2
add A12, #2
add A13, #2
ldc R4, @A11
ldw @[A12+0], R4
add A11, #2
add A12, #2
sub R6, #1
bnzd R6, %b1
ldc R4, @A11
pop A13
pop A12, A11
pop R6, R4
ret
.end⌨️ 快捷键说明
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