📄 asmlib.s
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INCLUDE "S5L9908F.REG"
include "asmdef.h"
_SUPPORT_KARAOKE_ equ 0
_SYSTEM_CLOCK_81M_ equ 1
;; .extern _CodecShared
AsmLib SECTION CODE
AsmLib
;
;*************************************************************************************************
; SUBROUTINES FOR DISABLING INTERRUPT
;*************************************************************************************************
;
;; PUBLIC _Set_CODECDONE
;;_Set_CODECDONE
;; ld a10,#_CodecShared+62 // CodecInvokeSyncFlag
;; ld r2, #0
;; CLRSR IE
;; ldb @[a10+0], r2 //CodecShared.CodecInvokeSyncFlag = CODEC_DONE;
;; SETSR IE
;; RET
;
;*************************************************************************************************
; SUBROUTINES FOR ENABLING INTERRUPT
;*************************************************************************************************
;
PUBLIC _EI
_ENABLE_ALL_INT::
_EXIT_CRITICAL::
_EI:
SETSR IE
JMP A14
;
;*************************************************************************************************
; SUBROUTINES FOR DISABLING INTERRUPT
;*************************************************************************************************
;
PUBLIC _DI
_ENTER_CRITICAL::
_DISABLE_ALL_INT::
_DI:
CLRSR IE
JMP A14
;
;*************************************************************************************************
; SUBROUTINES FOR POWER SAVING MODE
;*************************************************************************************************
;
PUBLIC _CPU_IDLE
_CPU_IDLE:
IDLE
NOP
JMP A14
PUBLIC _CPU_HALT
_CPU_HALT:
SYS #0x0f
NOP
JMP A14
PUBLIC _CPU_STOP
_CPU_STOP:
NOP
STOP
STOP
NOP
JMP A14
PUBLIC _NOP
_NOP:
NOP
JMP A14
//void Set_CPU_PLLCLOCK(unsigned int);
PUBLIC _Set_CPU_PLLCLOCK
_Set_CPU_PLLCLOCK:
ld r3, r0
LDB R0, @[A8+pllcon]
AND R0,#~4
LDB @[A8+pllcon],R0 // Set 32Khz
nop
LDW @[A8+pll0pms],R2 // Set New PLL Data
nop
// Lock Check
%80
LDB R0, @[A8+pllcon]
TST R0,#00000010b
brt %b80
ld R0,#30
%10 nop
nop
nop
nop
dec r0
brf %b10
nop
LDB R0, @[A8+pllcon]
OR R0,#4
LDB @[A8+pllcon],R0 // Start PLL0Out
nop
nop
nop
ld r0, r3
ret
;
;*************************************************************************************************
; SUBROUTINES FOR CLEARING IRQ0, IRQ1 PENDING BIT
;*************************************************************************************************
;
PUBLIC _CLEAR_IRQ0_PNDBIT
_CLEAR_IRQ0_PNDBIT:
// LD IIR0, R1
JMP A14
PUBLIC _CLEAR_IRQ1_PNDBIT
_CLEAR_IRQ1_PNDBIT:
// LD IIR1, R1
JMP A14
;
;*************************************************************************************************
; SUBROUTINES FOR INITIALIZING CPAD-WALTZ
;*************************************************************************************************
;
_INIT_CPADWALTZ::
// HFRS base address set //sfrs牢灏?
ld a8,#adm_base //0x2c0000
//ld a8,#0x2c0000 //0x2c0000
ld r0, #0x3c38
ldw r1, @[a8+sfrscfg] //0x46
ldw @[a8+sfrscfg], r0 //溜 3c38阑 2c0046俊 且寸 秦林绰 扁瓷 ...
// watchdog timer disable
ld a8, #wdt_base //0x390000
ld r0, #0x0
ld r1, #0x00a5
ldw @[a8+wdtcon], r0
ldw @[a8+wdtcon+2], r1
// Set Memory Size
ld a8, #miu_base //0x304000 phk TODAY 4 LINE COMMAND OUT
ld r0, #0x0020 //76KB SRAM phk
ldw @[a8+miussize], r0 //phk
ldw @[a8+miussize+2], r0 //phk
// miu sram parameter set
; ld a8, #0x304000
; ld r0, #0x0001
; ldw @[a8+0x10], r0
; ld r0, #0x0110
; ldw @[a8+0x10+2], r0 //0x800000FA
; ld a8, #0x30400c
; ld r0, #0x8000
; ld r1, #0xfa
; ldw @[a8] ,r0
; ldw @[a8+2] ,r1
ld a8, #0x304014
.if (_SYSTEM_CLOCK_81M_)
ld r0, #0x1
ld r1, #0x410 //for 81Mhze
.else
ld r0, #0x1
ld r1, #0x610 //for 81Mhze
.endif
ldw @[a8] ,r0
ldw @[a8+2] ,r1
// Set PLL Clock
ld a8, #clkunit_base //0x38a000
// 1. PLL count
//ld r0, #0x0
//ld r1, #0x1fff
//ldw @[a8+pll0lcnt], r0
//ldw @[a8+pll0lcnt+2], r1
//ldw @[a8+pll1lcnt], r0
//ldw @[a8+pll1lcnt+2], r1
ld r0,#0x0
ld r1,#0x1fff
ldw @[a8+0x18], r0 //PLL0LCNT high
ldw @[a8+0x18+2], r1 //low
ldw @[a8+0x1c], r0 //PLL1LCNT high
ldw @[a8+0x1c+2], r1 //low
ldw @[a8+0x20], r0 //PLL2LCNT high
ldw @[a8+0x20+2], r1 //low
// 2. Set PLL0 and PLL1 as 96.01MHz.
//ld r0,#0x001e
//ld r1,#0xe100
//ldw @[a8+pll0pms], r0
//ldw @[a8+pll0pms+2], r1
ld r0, #0x1E
ld r1, #0xE100
ldw @[a8+0x8], r0 //PLL0PMS high
ldw @[a8+0x8+2], r1 //PLL0PMS Low
//ld r0, #0x000B
// ld r0, #0x100B
// ld r1, #0x4600
// ldw @[a8+0x0c], r0 //PLL1PMS high
// ldw @[a8+0x0c+2], r1 //PLL1PMS Low
.if (_SYSTEM_CLOCK_81M_)
ld r0, #0xb //81Mhz
ld r1, #0x4600
.else
ld r0, #0x5 //108Mhz
ld r1, #0x3001
.endif
ldw @[a8+0x0c], r0 //PLL1PMS high
ldw @[a8+0x0c+2], r1 //PLL1PMS Low
//ld r0, #0x1572 //#0x0558
//ld r1, #0xcf00
ld r0, #0x1558
ld r1, #0xcf01
ldw @[a8+0x10], r0 //PLL2PMS high
ldw @[a8+0x10+2], r1 //PLL2PMS Low
// 3. Turn PLL0 and PLL1 on
//ld r0, #0x0
//ldw @[a8+pllcon], r0
//ld r0, #0x3
//ldw @[a8+pllcon+2], r0
ld r0, #0x0
ldw @[a8+0x2c], r0
ld r0, #0x7
ldw @[a8+0x2c+2], r0
// 5. Set PLL0 as main clock
//ld r0, #0x0001
//ldw @[a8+clkcon], r0
//ld r0, #0x5000
//ldw @[a8+clkcon+2],r0
//6. set clock power control
ld r0, #0x00ff
ld r1, #0xffff
ldw @[a8+0x30], r0 //PWRCON high
ldw @[a8+0x30+2], r1 //PWRCON Low
//7. set clock output control
ld r0, #0x0
ld r1, #0x179 //#0x0 //0x151
ldw @[a8+0x40], r0 //CKOCON high
ldw @[a8+0x40+2], r1 //CKOCON Low
//7. set clkcon output control
ld a8, #adm_base //0x2c0000
// 1. clk_mode
ld r0, #0x0
ldw @[a8+dhclkcon], r0
/*
ld r0, #0x5130
ld r1, #0x3273
ldw @[a8], r0 //ClkCON high
ldw @[a8+2], r1 //ClkCON Low
//7. set clkcon output control
ld r0, #0x0
ld r1, #0x33
ldw @[a8+4], r0 //ClkCON high
ldw @[a8+4+2], r1 //ClkCON Low
*/
//gpio setting
ld a8, #0x39e000 //0x38a000
//PCON0
ld r0,#0x9
ld r1,#0x2409
ldw @[a8], r0
ldw @[a8+2], r1
//PDATA0
ld r0,#0x0
ld r1,#0x0
ldw @[a8+0x04], r0
ldw @[a8+0x04+2], r1
//PCON1
ld r0,#0x9
ld r1,#0x2492
ldw @[a8+0x8], r0
ldw @[a8+0x8+2], r1
//PCON2
ld r0,#0x0
ld r1,#0x02
ldw @[a8+0x10], r0
ldw @[a8+0x10+2], r1
//PCON3
ld r0,#0x24
ld r1,#0x9412
ldw @[a8+0x18], r0
ldw @[a8+0x18+2], r1
// PDATA3
ld r0,#0x0
ld r1,#0x80
ldw @[a8+0x1c], r0
ldw @[a8+0x1c+2], r1
// Set Memory Region
// 0-1. Set-up I0-Base, D0-Base
ld a8, #adm_base //0x2c0000
ld r0, #0x0000 //region 0 base address //code memory肺 荤侩
ld r1, #0x0008 // size 256KB
ldw @[a8+r0cfg], r0
ldw @[a8+r0cfg+2], r1
ld r0, #0x0800 //resion 8 base address
ld r1, #0x0007 // size 128KB 08捞 size
ldw @[a8+r8cfg], r0 //physical address 8000000锅瘤俊 棱澜
ldw @[a8+r8cfg+2], r1
.if(1)
ld r0, #0x0802 //resion 9 base address = 0x0802d000
ld r1, #0x8D09 //resion 9 size = 512KB
.else
ld r0, #0x0802 //resion 9 base address = 0x0802d000
ld r1, #0xD009 //resion 9 size = 512KB
.endif
ldw @[a8+r9cfg], r0
ldw @[a8+r9cfg+2], r1
/*
ld r0, #0x0802 //region 9 base address
ld r1, #0x0006 // size 64KB 06捞 size
ldw @[a8+r9cfg], r0 //physical address 8020000 锅瘤俊 棱澜.
ldw @[a8+r9cfg+2], r1
ld r0, #0x0803 //region 10 base address
ld r1, #0x0009 // size 512KB 09啊 size
ldw @[a8+r10cfg], r0 //physical address 8030000 锅瘤俊 棱澜.
ldw @[a8+r10cfg+2], r1
*/
//ld r0, #0x080B //region 11 base address
//ld r1, #0x0001 // size 2KB 01捞 size
//ldw @[a8+r11cfg], r0 //physical address 8130000 锅瘤俊 棱澜.
//ldw @[a8+r11cfg+2], r1
.if(1) // changed by hspark 041221 for enable X,Y,S0,S1
//
// base & size information must be match with memmap.h information!!!
//
// region 12 = X memory region
.if (_SUPPORT_KARAOKE_)//********* 1==> Karaoke , 0 ==> no karaoke
ld r0, #0x0809// is not enough ,should be #0x0809
ld r1, #0x8406// is not enough ,should be #0x4906
.else
ld r0, #0X0809
ld r1, #0xC806//#0xA806<==for mp3 case
.endif
ldw @[a8+r12cfg], r0
ldw @[a8+r12cfg+2], r1
// region 13 = Y memory region
.if (_SUPPORT_KARAOKE_)//********* 1==> Karaoke , 0 ==> no karaoke
ld r0, #0x080A
ld r1, #0x3F06
.else
ld r0, #0x080A
ld r1, #0x5F06
.endif
ldw @[a8+r13cfg], r0
ldw @[a8+r13cfg+2], r1
// region 14 = S0 memory region
//ld r0, #0x080a // base address = 0x080a4e00 -0x4000 for tricky run of MPA
//ld r1, #0x0e03 // size = 8KB (3)
//look at here hk park
.if(1)//**********************************if 1, then big buffer ,if 0, then small buffer.
ld r0, #0x0801 // base address = 0x08020000
ld r1, #0x4008 // size = 256KB (3) This will be used by HW
.else
ld r0, #0x0802 // base address = 0x08020000
ld r1, #0x0008 // size = 256KB (3) This will be used by HW
.endif
ldw @[a8+r14cfg], r0
ldw @[a8+r14cfg+2], r1
// region 15 = S1 memory region
.if (_SUPPORT_KARAOKE_)//********* 1==> Karaoke , 0 ==> no karaoke
ld r0, #0x080A//#0x080a // base address = 0x080adc00
ld r1, #0xBE04//#0xdc04 // size = 16KB (4)
.else
ld r0, #0x080A // base address = 0x080adc00
ld r1, #0xdc04 // size = 16KB (4)
.endif
ldw @[a8+r15cfg], r0
ldw @[a8+r15cfg+2], r1
.endif
// 0-2. Enable R0/R8 region and R9 ,R 10
ldw r0, @[a8+recfg]
// or r0, #(1<<8) + (1<<0) // Enable R0/R8
// or r0, #(1<<8) + (1<<0) + (1<<9)// Enable R0/R8 /R9/R10
// or r0, #(1<<8) + (1<<0) + (1<<9) +(1<<10) // Enable R0/R8 /R9 /R10
or r0, #(1<<8) + (1<<0) // Enable R0/R8
or r0, #(1<<9) // Enable R9
.if(1) // changed by hspark 041221 for enable X,Y,S0,S1
or r0, #(1<<12) +(1<<13) +(1<<14) +(1<<15) // Enable R0/R8 /R9 /R10
.endif
// or r0, #(1<<8) + (1<<0) + (1<<9) +(1<<10)+(1<<11) // Enable R0/R8 /R9 /R10/R11
ldw @[a8+recfg], r0
// Invalidate Cache memory
ld r0, #0x111 // 0x144 // Invalidation for i/x/y-Cache
ldw @[a8+cachecon], r0 //0x48
//
%01 ldw r0, @[a8+cachestat] // 0x4c
and r0, #0x377
cmp eq,r0,#0x111
brt %b01
// Enable Cache i/x/y-mem
//ld r0, #0x222 // Enable i/x/y-Cache
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