host_interface.syr

Xilinx XC4VSX35为核心的 XtremeDSP Development Kit-IV 开发板的例程

#      LUT2_D                      : 3
#      LUT2_L                      : 1
#      LUT3                        : 165
#      LUT3_D                      : 13
#      LUT3_L                      : 8
#      LUT4                        : 278
#      LUT4_D                      : 16
#      LUT4_L                      : 84
#      MUXCY                       : 160
#      MUXCY_L                     : 40
#      MUXF5                       : 13
#      VCC                         : 1
#      XORCY                       : 137
# FlipFlops/Latches                : 461
#      FD                          : 12
#      FDC                         : 30
#      FDCE                        : 254
#      FDCPE                       : 5
#      FDE                         : 38
#      FDP                         : 15
#      FDPE                        : 105
#      FDR                         : 1
#      LDCE_1                      : 1
# RAMS                             : 2
#      RAM16X8S                    : 2
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGCTRL                    : 1
# IO Buffers                       : 49
#      IBUF                        : 4
#      IBUFG                       : 1
#      IOBUF                       : 32
#      OBUF                        : 12
# DCM_ADVs                         : 1
#      DCM_ADV                     : 1
# Others                           : 3
#      rm16x32d                    : 2
#      rm32x512_v4tgt              : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 4vsx35ff668-10 

 Number of Slices:                      407  out of  15360     2%  
 Number of Slice Flip Flops:            460  out of  30720     1%  
 Number of 4 input LUTs:                766  out of  30720     2%  
    Number used as logic:               750
    Number used as RAMs:                 16
 Number of IOs:                          49
 Number of bonded IOBs:                  49  out of    448    10%  
    IOB Flip Flops:                       1
 Number of GCLKs:                         2  out of     32     6%  
 Number of DCM_ADVs:                      1  out of      8    12%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------------------------------------------------------------+------------------------------------------------------+-------+
Clock Signal                                                                             | Clock buffer(FF name)                                | Load  |
-----------------------------------------------------------------------------------------+------------------------------------------------------+-------+
CLKB                                                                                     | Inst_dimeclk_module/DCM_INST/dcminst1:CLK0           | 345   |
DUMMYSIGNAL_not0002(DUMMYSIGNAL_not0002_wg_cy<7>:O)                                      | NONE(*)(DUMMYSIGNAL)                                 | 1     |
Inst_dimeclk_module/DCM_INST/clock2/cntout                                               | BUFG                                                 | 108   |
Inst_dimeclk_module/DCM_INST/clock2/clockwire(Inst_dimeclk_module/DCM_INST/clock2/omux:O)| NONE(*)(Inst_dimeclk_module/DCM_INST/clock2/divcnt_2)| 4     |
INT                                                                                      | NONE(Inst_dimeclk_module/DCM_INST/clock2/flop1)      | 5     |
-----------------------------------------------------------------------------------------+------------------------------------------------------+-------+
(*) These 2 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
-------------------------------------------------------------------------------------------------------------+----------------------------------------------------+-------+
Control Signal                                                                                               | Buffer(FF name)                                    | Load  |
-------------------------------------------------------------------------------------------------------------+----------------------------------------------------+-------+
H1_IFACE/RST(H1_IFACE/RSTi1_INV_0:O)                                                                         | NONE(H1_IFACE/H2_DMA_CTRL/COUNT1_28)               | 199   |
H1_IFACE/SYNC_RSTid2(H1_IFACE/SYNC_RSTid2:Q)                                                                 | NONE(REG1_0)                                       | 132   |
CLKB                                                                                                         | IBUFG                                              | 20    |
CLKBi(Inst_dimeclk_module/DCM_INST/bufginst:O)                                                               | BUFGCTRL(Inst_dimeclk_module/DCM_INST/cont3/cntr_9)| 20    |
Inst_dimeclk_module/DCM_INST/cont2_not0000(Inst_dimeclk_module/DCM_INST/cont2_not00001_INV_0:O)              | NONE(Inst_dimeclk_module/DCM_INST/cont2/cntr_2)    | 20    |
H1_IFACE/H2_DMA_CTRL/H1_INFIFO/N_EMPTYi_or0000(H1_IFACE/H2_DMA_CTRL/H1_INFIFO/N_EMPTYi_or00001:O)            | NONE(H1_IFACE/H2_DMA_CTRL/H1_INFIFO/FIFO_GAGE_0)   | 14    |
Inst_dimeclk_module/DCM_INST/clock2/bufcon0(Inst_dimeclk_module/DCM_INST/clock2/flop4:Q)                     | NONE(Inst_dimeclk_module/DCM_INST/clock2/flop1)    | 1     |
Inst_dimeclk_module/DCM_INST/clock2/bufcon1(Inst_dimeclk_module/DCM_INST/clock2/flop1:Q)                     | NONE(Inst_dimeclk_module/DCM_INST/clock2/flop2)    | 1     |
Inst_dimeclk_module/DCM_INST/clock2/bufcon2(Inst_dimeclk_module/DCM_INST/clock2/flop2:Q)                     | NONE(Inst_dimeclk_module/DCM_INST/clock2/flop3)    | 1     |
Inst_dimeclk_module/DCM_INST/clock2/bufcon3(Inst_dimeclk_module/DCM_INST/clock2/flop3:Q)                     | NONE(Inst_dimeclk_module/DCM_INST/clock2/flop4)    | 1     |
Inst_dimeclk_module/DCM_INST/clock2/flop1_not0000(Inst_dimeclk_module/DCM_INST/clock2/flop1_not00001_INV_0:O)| NONE(Inst_dimeclk_module/DCM_INST/clock2/flop1)    | 1     |
Inst_dimeclk_module/DCM_INST/clock2/flop2_not0000(Inst_dimeclk_module/DCM_INST/clock2/flop2_not00001_INV_0:O)| NONE(Inst_dimeclk_module/DCM_INST/clock2/flop2)    | 1     |
Inst_dimeclk_module/DCM_INST/clock2/flop3_not0000(Inst_dimeclk_module/DCM_INST/clock2/flop3_not00001_INV_0:O)| NONE(Inst_dimeclk_module/DCM_INST/clock2/flop3)    | 1     |
Inst_dimeclk_module/DCM_INST/clock2/flop4_not0000(Inst_dimeclk_module/DCM_INST/clock2/flop4_not00001_INV_0:O)| NONE(Inst_dimeclk_module/DCM_INST/clock2/flop4)    | 1     |
Inst_dimeclk_module/DCM_INST/rst_clear(Inst_dimeclk_module/DCM_INST/rst_clear:Q)                             | NONE(Inst_dimeclk_module/DCM_INST/rstflop1)        | 1     |
RST_EXT(RST_EXT1_INV_0:O)                                                                                    | NONE(Inst_dimeclk_module/DCM_INST/rstflop1)        | 1     |
-------------------------------------------------------------------------------------------------------------+----------------------------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -10

   Minimum period: 4.954ns (Maximum Frequency: 201.847MHz)
   Minimum input arrival time before clock: 4.570ns
   Maximum output required time after clock: 5.977ns
   Maximum combinational path delay: 0.780ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'CLKB'
  Clock period: 4.954ns (frequency: 201.847MHz)
  Total number of paths / destination ports: 14606 / 607
-------------------------------------------------------------------------
Delay:               4.954ns (Levels of Logic = 6)
  Source:            H1_IFACE/H1_MAIN_CTRL/WR_DMAid1 (FF)
  Destination:       H1_IFACE/H1_MAIN_CTRL/DATA_READY (FF)
  Source Clock:      CLKB rising
  Destination Clock: CLKB rising

  Data Path: H1_IFACE/H1_MAIN_CTRL/WR_DMAid1 to H1_IFACE/H1_MAIN_CTRL/DATA_READY
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              1   0.360   0.741  H1_IFACE/H1_MAIN_CTRL/WR_DMAid1 (H1_IFACE/H1_MAIN_CTRL/WR_DMAid1)
     LUT4:I0->O            8   0.195   0.608  H1_IFACE/H1_MAIN_CTRL/WR_DMA1 (H1_IFACE/WR_DMA)
     LUT4:I3->O            1   0.195   0.000  H1_IFACE/H2_DMA_CTRL/TERM_CNT_or0001_wg_lut<8> (H1_IFACE/H2_DMA_CTRL/TERM_CNT_or0001_wg_lut<8>)
     MUXCY:S->O           20   0.691   0.809  H1_IFACE/H2_DMA_CTRL/TERM_CNT_or0001_wg_cy<8> (H1_IFACE/H2_DMA_CTRL/TERM_CNT_or0001_wg_cy<8>)
     LUT3:I2->O            1   0.195   0.585  H1_IFACE/H1_MAIN_CTRL/DATA_READY_mux00005 (H1_IFACE/H1_MAIN_CTRL/DATA_READY_mux00005)
     LUT4_L:I2->LO         1   0.195   0.163  H1_IFACE/H1_MAIN_CTRL/DATA_READY_mux000018 (H1_IFACE/H1_MAIN_CTRL/DATA_READY_mux000018)
     LUT4:I3->O            1   0.195   0.000  H1_IFACE/H1_MAIN_CTRL/DATA_READY_mux000048 (H1_IFACE/H1_MAIN_CTRL/DATA_READY_mux0000)
     FDC:D                     0.022          H1_IFACE/H1_MAIN_CTRL/DATA_READY
    ----------------------------------------
    Total                      4.954ns (2.048ns logic, 2.906ns route)
                                       (41.3% logic, 58.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_dimeclk_module/DCM_INST/clock2/cntout'
  Clock period: 4.470ns (frequency: 223.728MHz)
  Total number of paths / destination ports: 2129 / 209
-------------------------------------------------------------------------
Delay:               4.470ns (Levels of Logic = 3)
  Source:            Inst_dimeclk_module/DCM_INST/clksw1 (FF)
  Destination:       Inst_dimeclk_module/DCM_INST/state_drp_3 (FF)
  Source Clock:      Inst_dimeclk_module/DCM_INST/clock2/cntout rising
  Destination Clock: Inst_dimeclk_module/DCM_INST/clock2/cntout rising

  Data Path: Inst_dimeclk_module/DCM_INST/clksw1 to Inst_dimeclk_module/DCM_INST/state_drp_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               3   0.360   0.703  Inst_dimeclk_module/DCM_INST/clksw1 (Inst_dimeclk_module/DCM_INST/clksw1)
     LUT3_D:I0->O         14   0.195   0.716  Inst_dimeclk_module/DCM_INST/sw_bufg_or000011 (Inst_dimeclk_module/DCM_INST/N12)
     LUT4:I3->O           42   0.195   1.192  Inst_dimeclk_module/DCM_INST/ram_addr_FFd3-In41 (Inst_dimeclk_module/DCM_INST/ram_addr_and0006)
     LUT3:I1->O            4   0.195   0.374  Inst_dimeclk_module/DCM_INST/state_drp_not00022 (Inst_dimeclk_module/DCM_INST/state_drp_not0002)
     FDE:CE                    0.540          Inst_dimeclk_module/DCM_INST/state_drp_0
    ----------------------------------------
    Total                      4.470ns (1.485ns logic, 2.985ns route)
                                       (33.2% logic, 66.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'Inst_dimeclk_module/DCM_INST/clock2/clockwire'
  Clock period: 2.160ns (frequency: 462.931MHz)
  Total number of paths / destination ports: 10 / 5
-------------------------------------------------------------------------
Delay:               2.160ns (Levels of Logic = 1)
  Source:            Inst_dimeclk_module/DCM_INST/clock2/divcnt_2 (FF)
  Destination:       Inst_dimeclk_module/DCM_INST/clock2/cntout (FF)
  Source Clock:      Inst_dimeclk_module/DCM_INST/clock2/clockwire rising
  Destination Clock: Inst_dimeclk_module/DCM_INST/clock2/clockwire rising

  Data Path: Inst_dimeclk_module/DCM_INST/clock2/divcnt_2 to Inst_dimeclk_module/DCM_INST/clock2/cntout
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               2   0.360   0.705  Inst_dimeclk_module/DCM_INST/clock2/divcnt_2 (Inst_dimeclk_module/DCM_INST/clock2/divcnt_2)
     LUT3:I0->O            1   0.195   0.360  Inst_dimeclk_module/DCM_INST/clock2/cntout_cmp_eq00001 (Inst_dimeclk_module/DCM_INST/clock2/cntout_not0002_inv)
     FDE:CE                    0.540          Inst_dimeclk_module/DCM_INST/clock2/cntout
    ----------------------------------------
    Total                      2.160ns (1.095ns logic, 1.065ns route)
                                       (50.7% logic, 49.3% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLKB'
  Total number of paths / desti