host_interface.syr

Xilinx XC4VSX35为核心的 XtremeDSP Development Kit-IV 开发板的例程

    Found 1-bit xor2 for signal <ECOMP_5$xor0000> created at line 438.
    Found 1-bit xor2 for signal <ECOMP_6$xor0000> created at line 439.
    Found 1-bit xor2 for signal <ECOMP_7$xor0000> created at line 440.
    Found 1-bit xor2 for signal <ECOMP_8$xor0000> created at line 441.
    Found 1-bit register for signal <EMPTY>.
    Found 1-bit xor2 for signal <FCOMP_0$xor0000> created at line 475.
    Found 1-bit xor2 for signal <FCOMP_1$xor0000> created at line 476.
    Found 1-bit xor2 for signal <FCOMP_2$xor0000> created at line 477.
    Found 1-bit xor2 for signal <FCOMP_3$xor0000> created at line 478.
    Found 1-bit xor2 for signal <FCOMP_4$xor0000> created at line 479.
    Found 1-bit xor2 for signal <FCOMP_5$xor0000> created at line 480.
    Found 1-bit xor2 for signal <FCOMP_6$xor0000> created at line 481.
    Found 1-bit xor2 for signal <FCOMP_7$xor0000> created at line 482.
    Found 1-bit xor2 for signal <FCOMP_8$xor0000> created at line 483.
    Found 1-bit register for signal <FULL>.
    Found 9-bit up counter for signal <READ_ADDR>.
    Found 9-bit register for signal <READ_ADDRGRAY>.
    Found 9-bit register for signal <READ_LASTGRAY>.
    Found 9-bit register for signal <READ_NEXTGRAY>.
    Found 1-bit xor2 for signal <READ_NEXTGRAY_0$xor0000> created at line 223.
    Found 1-bit xor2 for signal <READ_NEXTGRAY_1$xor0000> created at line 222.
    Found 1-bit xor2 for signal <READ_NEXTGRAY_2$xor0000> created at line 221.
    Found 1-bit xor2 for signal <READ_NEXTGRAY_3$xor0000> created at line 220.
    Found 1-bit xor2 for signal <READ_NEXTGRAY_4$xor0000> created at line 219.
    Found 1-bit xor2 for signal <READ_NEXTGRAY_5$xor0000> created at line 218.
    Found 1-bit xor2 for signal <READ_NEXTGRAY_6$xor0000> created at line 217.
    Found 1-bit xor2 for signal <READ_NEXTGRAY_7$xor0000> created at line 216.
    Found 5-bit register for signal <STATUS>.
    Found 2-bit comparator equal for signal <STATUS_0$cmp_eq0000> created at line 313.
    Found 9-bit up counter for signal <WRITE_ADDR>.
    Found 9-bit register for signal <WRITE_ADDRGRAY>.
    Found 9-bit register for signal <WRITE_NEXTGRAY>.
    Found 1-bit xor2 for signal <WRITE_NEXTGRAY_0$xor0000> created at line 282.
    Found 1-bit xor2 for signal <WRITE_NEXTGRAY_1$xor0000> created at line 281.
    Found 1-bit xor2 for signal <WRITE_NEXTGRAY_2$xor0000> created at line 280.
    Found 1-bit xor2 for signal <WRITE_NEXTGRAY_3$xor0000> created at line 279.
    Found 1-bit xor2 for signal <WRITE_NEXTGRAY_4$xor0000> created at line 278.
    Found 1-bit xor2 for signal <WRITE_NEXTGRAY_5$xor0000> created at line 277.
    Found 1-bit xor2 for signal <WRITE_NEXTGRAY_6$xor0000> created at line 276.
    Found 1-bit xor2 for signal <WRITE_NEXTGRAY_7$xor0000> created at line 275.
    Summary:
	inferred   2 Counter(s).
	inferred  25 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <SYNCFIFO> synthesized.


Synthesizing Unit <ringregosc>.
    Related source file is "E:/host_interface_basic/source/ringregosc.vhd".
    Found 1-bit register for signal <cntout>.
    Found 3-bit up counter for signal <divcnt>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <ringregosc> synthesized.


Synthesizing Unit <FWFRFF_32>.
    Related source file is "E:/host_interface_basic/source/fwfrff_32.vhd".
    Found 1-bit register for signal <EMPTYi>.
    Found 5-bit updown counter for signal <FIFO_GAGE>.
    Found 1-bit register for signal <FULLi>.
    Found 1-bit register for signal <N_EMPTYi>.
    Found 5-bit comparator less for signal <N_EMPTYi$cmp_lt0000> created at line 166.
    Found 1-bit register for signal <N_FULLi>.
    Found 5-bit comparator greater for signal <N_FULLi$cmp_gt0000> created at line 173.
    Summary:
	inferred   1 Counter(s).
	inferred   4 D-type flip-flop(s).
	inferred   2 Comparator(s).
Unit <FWFRFF_32> synthesized.


Synthesizing Unit <dcm_standby>.
    Related source file is "E:/host_interface_basic/source/dcm_standby.vhd".
    Found finite state machine <FSM_1> for signal <ram_addr>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 141                                            |
    | Inputs             | 11                                             |
    | Outputs            | 8                                              |
    | Clock              | clk_osc (rising_edge)                          |
    | Clock enable       | ram_addr$not0000 (positive)                    |
    | Power Up State     | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Using one-hot encoding for signal <state_drp>.
    Found 1-bit register for signal <clk_en1>.
    Found 1-bit register for signal <clk_en2>.
    Found 1-bit register for signal <clk_en3>.
    Found 1-bit register for signal <clksw1>.
    Found 1-bit register for signal <clksw2>.
    Found 1-bit register for signal <clksw3>.
    Found 1-bit register for signal <dcmrst>.
    Found 7-bit register for signal <drp_addr>.
    Found 1-bit register for signal <drp_en>.
    Found 16-bit register for signal <drp_in>.
    Found 1-bit register for signal <drp_we>.
    Found 1-bit register for signal <protct_drp_sav>.
    Found 1-bit register for signal <ram_we>.
    Found 1-bit register for signal <rst_clear>.
    Found 3-bit register for signal <rstcnt>.
    Found 3-bit adder for signal <rstcnt$addsub0000> created at line 276.
    Found 4-bit register for signal <state_drp>.
    Found 1-bit register for signal <sw_bufg>.
    Found 1-bit register for signal <usr_rst>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  44 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <dcm_standby> synthesized.


Synthesizing Unit <DMA_CTRL>.
    Related source file is "E:/host_interface_basic/source/dma_ctrl.vhd".
WARNING:Xst:647 - Input <DMA_ENABLE> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1780 - Signal <OUTFIFO_STATUS> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <OUTFIFO_FULL> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <INFIFO_STATUS> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <INFIFO_FULL> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <FIFO_RST> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <DMA_RSTi> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
    Found 32-bit tristate buffer for signal <DMA_DATA>.
    Found 32-bit down counter for signal <COUNT1>.
    Found 32-bit down counter for signal <COUNT2>.
    Summary:
	inferred   2 Counter(s).
	inferred  32 Tristate(s).
Unit <DMA_CTRL> synthesized.


Synthesizing Unit <dimeclk_module>.
    Related source file is "E:/download_material/virtex4_board/XTremeDSP_developmentIV/Examples/host_interface_basic/ise/host_interface/dimeclk_module_mod.vhd".
Unit <dimeclk_module> synthesized.


Synthesizing Unit <SV_IFACE>.
    Related source file is "E:/host_interface_basic/source/sv_iface.vhd".
WARNING:Xst:646 - Signal <BUSYd1> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 1-bit register for signal <SYNC_RSTi>.
    Found 1-bit register for signal <SYNC_RSTid1>.
    Found 1-bit register for signal <SYNC_RSTid2>.
    Summary:
	inferred   3 D-type flip-flop(s).
Unit <SV_IFACE> synthesized.


Synthesizing Unit <host_interface>.
    Related source file is "E:/host_interface_basic/source/host_interface.vhd".
WARNING:Xst:646 - Signal <FIFO_STATUS<4>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <FIFO_STATUS<2:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <EMPTYd2> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <EMPTYd1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <AS_DSld2> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <AS_DSld1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <ADDRESS<30:4>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:737 - Found 1-bit latch for signal <DUMMYSIGNAL>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
    Found 32-bit tristate buffer for signal <DATA>.
    Found 32-bit tristate buffer for signal <DMA_DATA>.
    Found 1-bit register for signal <DMA_WEN>.
    Found 32-bit register for signal <REG1>.
    Found 32-bit register for signal <REG2>.
    Found 1-bit register for signal <RST_INTl>.
    Summary:
	inferred  66 D-type flip-flop(s).
	inferred  96 Tristate(s).
Unit <host_interface> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 1
 3-bit adder                                           : 1
# Counters                                             : 14
 20-bit up counter                                     : 3
 3-bit up counter                                      : 1
 32-bit down counter                                   : 2
 4-bit updown counter                                  : 4
 5-bit updown counter                                  : 2
 9-bit up counter                                      : 2
# Registers                                            : 91
 1-bit register                                        : 79
 16-bit register                                       : 1
 3-bit register                                        : 1
 32-bit register                                       : 5
 4-bit register                                        : 1
 7-bit register                                        : 1
 9-bit register                                        : 3
# Latches                                              : 1
 1-bit latch                                           : 1
# Comparators                                          : 5
 2-bit comparator equal                                : 1
 5-bit comparator greater                              : 2
 5-bit comparator less                                 : 2
# Tristates                                            : 9
 32-bit tristate buffer                                : 9
# Xors                                                 : 52
 1-bit xor2                                            : 52