host_interface.syr

Xilinx XC4VSX35为核心的 XtremeDSP Development Kit-IV 开发板的例程

WARNING:Xst:753 - "E:/download_material/virtex4_board/XTremeDSP_developmentIV/Examples/host_interface_basic/ise/host_interface/dimeclk_module_mod.vhd" line 169: Unconnected output port 'CLKFX' of component 'dcm_standby'.
WARNING:Xst:753 - "E:/download_material/virtex4_board/XTremeDSP_developmentIV/Examples/host_interface_basic/ise/host_interface/dimeclk_module_mod.vhd" line 169: Unconnected output port 'CLKFX180' of component 'dcm_standby'.
WARNING:Xst:753 - "E:/download_material/virtex4_board/XTremeDSP_developmentIV/Examples/host_interface_basic/ise/host_interface/dimeclk_module_mod.vhd" line 169: Unconnected output port 'DO' of component 'dcm_standby'.
WARNING:Xst:753 - "E:/download_material/virtex4_board/XTremeDSP_developmentIV/Examples/host_interface_basic/ise/host_interface/dimeclk_module_mod.vhd" line 169: Unconnected output port 'PSDONE' of component 'dcm_standby'.
Entity <dimeclk_module> analyzed. Unit <dimeclk_module> generated.

Analyzing Entity <dcm_standby> in library <work> (Architecture <dcm_standby>).
    Set property "CLOCK_SIGNAL = FALSE" for signal <clk_osc>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/dcm_standby.vhd" line 162: Instantiating black box module <DCM_ADV>.
    Set user-defined property "DCM_AUTOCALIBRATION =  FALSE" for instance <dcminst1> in unit <dcm_standby>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/dcm_standby.vhd" line 189: Instantiating black box module <BUFGCTRL>.
WARNING:Xst:38 - Value "none" of property "CLOCK_SIGNAL" not applicable.
WARNING:Xst:2211 - "E:/host_interface_basic/source/dcm_standby.vhd" line 230: Instantiating black box module <RAM16X8S>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/dcm_standby.vhd" line 241: Instantiating black box module <RAM16X8S>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/dcm_standby.vhd" line 255: Instantiating black box module <FDCPE>.
Entity <dcm_standby> analyzed. Unit <dcm_standby> generated.

Analyzing Entity <ringregosc> in library <work> (Architecture <ringregosc>).
WARNING:Xst:38 - Value "none" of property "CLOCK_SIGNAL" not applicable.
WARNING:Xst:2211 - "E:/host_interface_basic/source/ringregosc.vhd" line 52: Instantiating black box module <FDCPE>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/ringregosc.vhd" line 62: Instantiating black box module <FDCPE>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/ringregosc.vhd" line 72: Instantiating black box module <FDCPE>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/ringregosc.vhd" line 82: Instantiating black box module <FDCPE>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/ringregosc.vhd" line 92: Instantiating black box module <MUXF5>.
Entity <ringregosc> analyzed. Unit <ringregosc> generated.

Analyzing Entity <counter> in library <work> (Architecture <counter>).
Entity <counter> analyzed. Unit <counter> generated.

Analyzing generic Entity <SV_IFACE> in library <work> (Architecture <SV_IFACE_arch>).
	BLOCK_SIZEg = 4
	NUM_BLOCKSg = 1
	NUM_REGSg = 3
Entity <SV_IFACE> analyzed. Unit <SV_IFACE> generated.

Analyzing generic Entity <IF_MAIN> in library <work> (Architecture <if_main_arch>).
	BLOCK_SIZEg = 4
	NUM_BLOCKSg = 1
	NUM_REGSg = 3
Entity <IF_MAIN> analyzed. Unit <IF_MAIN> generated.

Analyzing Entity <DMA_CTRL> in library <work> (Architecture <DMA_CTRL_arch>).
WARNING:Xst:753 - "E:/host_interface_basic/source/dma_ctrl.vhd" line 144: Unconnected output port 'FULL' of component 'FWFRFF_32'.
WARNING:Xst:753 - "E:/host_interface_basic/source/dma_ctrl.vhd" line 144: Unconnected output port 'N_EMPTY' of component 'FWFRFF_32'.
WARNING:Xst:753 - "E:/host_interface_basic/source/dma_ctrl.vhd" line 193: Unconnected output port 'FULL' of component 'FWFRFF_32'.
WARNING:Xst:753 - "E:/host_interface_basic/source/dma_ctrl.vhd" line 193: Unconnected output port 'N_EMPTY' of component 'FWFRFF_32'.
Entity <DMA_CTRL> analyzed. Unit <DMA_CTRL> generated.

Analyzing generic Entity <FWFRFF_32> in library <work> (Architecture <FWFRFF_32_arch>).
	ATLEASTNEMPTYg = 8
	ATLEASTNFULLg = 8
	NEEDBACKUPg = 0
WARNING:Xst:753 - "E:/host_interface_basic/source/fwfrff_32.vhd" line 80: Unconnected output port 'SPO' of component 'rm16x32d'.
WARNING:Xst:2211 - "E:/host_interface_basic/source/fwfrff_32.vhd" line 80: Instantiating black box module <rm16x32d>.
Entity <FWFRFF_32> analyzed. Unit <FWFRFF_32> generated.

Analyzing Entity <FIFOCNT4> in library <work> (Architecture <FIFOCNT4_arch>).
Entity <FIFOCNT4> analyzed. Unit <FIFOCNT4> generated.

Analyzing Entity <SYNCFIFO> in library <work> (Architecture <SYNCFIFO_ARCH>).
WARNING:Xst:753 - "E:/host_interface_basic/source/syncfifo.vhd" line 131: Unconnected output port 'doutb' of component 'rm32x512_v4tgt'.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 131: Instantiating black box module <rm32x512_v4tgt>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 443: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 444: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 445: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 446: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 447: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 448: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 449: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 450: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 451: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 452: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 464: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 465: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 466: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 467: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 468: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 469: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 470: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 471: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 472: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 473: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 485: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 486: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 487: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 488: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 489: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 490: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 491: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 492: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 493: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 494: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 506: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 507: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 508: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 509: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 510: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 511: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 512: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 513: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 514: Instantiating black box module <MUXCY_L>.
WARNING:Xst:2211 - "E:/host_interface_basic/source/syncfifo.vhd" line 515: Instantiating black box module <MUXCY_L>.
Entity <SYNCFIFO> analyzed. Unit <SYNCFIFO> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <counter>.
    Related source file is "E:/host_interface_basic/source/counter.vhd".
    Found 20-bit up counter for signal <cntr>.
    Summary:
	inferred   1 Counter(s).
Unit <counter> synthesized.


Synthesizing Unit <IF_MAIN>.
    Related source file is "E:/host_interface_basic/source/if_main.vhd".
WARNING:Xst:1780 - Signal <DVALIDd2> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <DVALIDd1> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <DVALID> is used but never assigned. This sourceless signal will be automatically connected to value 0.
    Found finite state machine <FSM_0> for signal <SM_STATE>.
    -----------------------------------------------------------------------
    | States             | 17                                             |
    | Transitions        | 44                                             |
    | Inputs             | 12                                             |
    | Outputs            | 17                                             |
    | Clock              | CLK (rising_edge)                              |
    | Reset              | RST (positive)                                 |
    | Reset type         | asynchronous                                   |
    | Reset State        | rst_state                                      |
    | Power Up State     | rst_state                                      |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 32-bit tristate buffer for signal <ADIO>.
    Found 32-bit tristate buffer for signal <DATA>.
    Found 32-bit register for signal <ADDRESSi>.
    Found 1-bit register for signal <AS_DSl_IN>.
    Found 1-bit register for signal <BUSYd1>.
    Found 11-bit register for signal <CSR<10:0>>.
    Found 1-bit register for signal <DATA_READY>.
    Found 32-bit register for signal <DATAIN>.
    Found 32-bit register for signal <DATAOUT>.
    Found 1-bit register for signal <EMPTYd1>.
    Found 1-bit register for signal <RD_DMAi>.
    Found 1-bit register for signal <RDl_WRi>.
    Found 1-bit register for signal <RENl_WENli>.
    Found 1-bit register for signal <WR_DMAi>.
    Found 1-bit register for signal <WR_DMAid1>.
    Found 1-bit register for signal <WR_REG_WRd1>.
    Found 1-bit register for signal <WRITE_STROBEid1>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred 118 D-type flip-flop(s).
	inferred 160 Tristate(s).
Unit <IF_MAIN> synthesized.


Synthesizing Unit <FIFOCNT4>.
    Related source file is "E:/host_interface_basic/source/fifocnt4.vhd".
    Found 4-bit updown counter for signal <COUNT>.
    Found 1-bit register for signal <SYNCRST>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
Unit <FIFOCNT4> synthesized.


Synthesizing Unit <SYNCFIFO>.
    Related source file is "E:/host_interface_basic/source/syncfifo.vhd".
WARNING:Xst:1780 - Signal <TEMPO4> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <TEMPO3> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <TEMPO2> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <TEMPO1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
    Found 1-bit xor2 for signal <AECOMP_0$xor0000> created at line 454.
    Found 1-bit xor2 for signal <AECOMP_1$xor0000> created at line 455.
    Found 1-bit xor2 for signal <AECOMP_2$xor0000> created at line 456.
    Found 1-bit xor2 for signal <AECOMP_3$xor0000> created at line 457.
    Found 1-bit xor2 for signal <AECOMP_4$xor0000> created at line 458.
    Found 1-bit xor2 for signal <AECOMP_5$xor0000> created at line 459.
    Found 1-bit xor2 for signal <AECOMP_6$xor0000> created at line 460.
    Found 1-bit xor2 for signal <AECOMP_7$xor0000> created at line 461.
    Found 1-bit xor2 for signal <AECOMP_8$xor0000> created at line 462.
    Found 1-bit xor2 for signal <AFCOMP_0$xor0000> created at line 496.
    Found 1-bit xor2 for signal <AFCOMP_1$xor0000> created at line 497.
    Found 1-bit xor2 for signal <AFCOMP_2$xor0000> created at line 498.
    Found 1-bit xor2 for signal <AFCOMP_3$xor0000> created at line 499.
    Found 1-bit xor2 for signal <AFCOMP_4$xor0000> created at line 500.
    Found 1-bit xor2 for signal <AFCOMP_5$xor0000> created at line 501.
    Found 1-bit xor2 for signal <AFCOMP_6$xor0000> created at line 502.
    Found 1-bit xor2 for signal <AFCOMP_7$xor0000> created at line 503.
    Found 1-bit xor2 for signal <AFCOMP_8$xor0000> created at line 504.
    Found 1-bit xor2 for signal <ECOMP_0$xor0000> created at line 433.
    Found 1-bit xor2 for signal <ECOMP_1$xor0000> created at line 434.
    Found 1-bit xor2 for signal <ECOMP_2$xor0000> created at line 435.
    Found 1-bit xor2 for signal <ECOMP_3$xor0000> created at line 436.
    Found 1-bit xor2 for signal <ECOMP_4$xor0000> created at line 437.