dimeclk_module_mod.vhd

Xilinx XC4VSX35为核心的 XtremeDSP Development Kit-IV 开发板的例程

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 6.3.02i
--  \   \         Application : 
--  /   /         Filename : dimeclk_module.vhd
-- /___/   /\     Timestamp : 11/30/2004 13:37:17
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: dimeclk_module
--
-- Module dimeclk_module
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity dimeclk_module is
   port ( CLKIN_IN        : in    std_logic; 
          RST_IN          : in    std_logic; 
          CLKIN_IBUFG_OUT : out   std_logic; 
          CLK0_OUT        : out   std_logic; 
          LOCKED_OUT      : out   std_logic);
end dimeclk_module;

architecture BEHAVIORAL of dimeclk_module is
   signal CLKFB_IN        : std_logic;
   signal CLKIN_IBUFG     : std_logic;
   signal CLK0_BUF        : std_logic;
   signal GND             : std_logic;
   component IBUFG
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   
   component BUFG
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   
   component DCM
      generic( CLK_FEEDBACK : string :=  "1X";
               CLKDV_DIVIDE : real :=  2.000000;
               CLKFX_DIVIDE : integer :=  1;
               CLKFX_MULTIPLY : integer :=  4;
               CLKIN_DIVIDE_BY_2 : boolean :=  FALSE;
               CLKIN_PERIOD : real :=  0.000000;
               CLKOUT_PHASE_SHIFT : string :=  "NONE";
               DESKEW_ADJUST : string :=  "SYSTEM_SYNCHRONOUS";
               DFS_FREQUENCY_MODE : string :=  "LOW";
               DLL_FREQUENCY_MODE : string :=  "LOW";
               DUTY_CYCLE_CORRECTION : boolean :=  TRUE;
               FACTORY_JF : bit_vector :=  x"C080";
               PHASE_SHIFT : integer :=  0;
               STARTUP_WAIT : boolean :=  FALSE;
               DSS_MODE : string :=  "NONE";
               MAXPERCLKIN : time :=  1000000 ps;
               MAXPERPSCLK : time :=  100000000 ps;
               SIM_CLKIN_CYCLE_JITTER : time :=  300 ps;
               SIM_CLKIN_PERIOD_JITTER : time :=  1000 ps);
      port ( CLKIN    : in    std_logic; 
             CLKFB    : in    std_logic; 
             RST      : in    std_logic; 
             PSEN     : in    std_logic; 
             PSINCDEC : in    std_logic; 
             PSCLK    : in    std_logic; 
             DSSEN    : in    std_logic; 
             CLK0     : out   std_logic; 
             CLK90    : out   std_logic; 
             CLK180   : out   std_logic; 
             CLK270   : out   std_logic; 
             CLKDV    : out   std_logic; 
             CLK2X    : out   std_logic; 
             CLK2X180 : out   std_logic; 
             CLKFX    : out   std_logic; 
             CLKFX180 : out   std_logic; 
             STATUS   : out   std_logic_vector (7 downto 0); 
             LOCKED   : out   std_logic; 
             PSDONE   : out   std_logic);
   end component;
   
   --This component is being used for V4 silicon to handle the addition of the
   --new clocking constraints. This design was released by Xilinx. It handles the 
   --constraints for stopping the clock for more than 100ms and also for holding
   --the design in reset for more than 10 sec. 
   component dcm_standby IS
      PORT (
         CLK0                    : OUT std_logic;   
         CLK180                  : OUT std_logic;   
         CLK270                  : OUT std_logic;   
         CLK2X                   : OUT std_logic;   
         CLK2X180                : OUT std_logic;   
         CLK90                   : OUT std_logic;   
         CLKDV                   : OUT std_logic;   
         CLKFX                   : OUT std_logic;   
         CLKFX180                : OUT std_logic;   
         DO                      : OUT std_logic_vector(15 DOWNTO 0);   
         LOCKED                  : OUT  std_logic;   
         PSDONE                  : OUT std_logic;   
         CLKFB                   : IN std_logic;   
         CLKIN                   : IN std_logic;   
         PSCLK                   : IN std_logic;   
         PSEN                    : IN std_logic;        
         PSINCDEC                : IN std_logic;   
         RST                     : IN std_logic);
END component;
   
begin
   GND <= '0';
   CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
   CLK0_OUT <= CLKFB_IN;
   CLKIN_IBUFG_INST : IBUFG
      port map (I=>CLKIN_IN,      
                O=>CLKIN_IBUFG);
   
   --CLK0_BUFG_INST : BUFG
   --   port map (I=>CLK0_BUF,      
   --             O=>CLKFB_IN);
      CLKFB_IN <= CLK0_BUF;
   
   --DCM_INST : DCM
   --generic map( CLK_FEEDBACK => "1X",
   --         CLKDV_DIVIDE => 2.000000,
   --         CLKFX_DIVIDE => 1,
   --         CLKFX_MULTIPLY => 4,
   --         CLKIN_DIVIDE_BY_2 => FALSE,
   --         CLKIN_PERIOD => 12.500000,
   --         CLKOUT_PHASE_SHIFT => "NONE",
   --         DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
   --         DFS_FREQUENCY_MODE => "LOW",
   --         DLL_FREQUENCY_MODE => "LOW",
   --         DUTY_CYCLE_CORRECTION => TRUE,
   --         FACTORY_JF => x"C080",
   --         PHASE_SHIFT => 0,
   --         STARTUP_WAIT => FALSE)
   --   port map (CLKFB=>CLKFB_IN,      
   --             CLKIN=>CLKIN_IBUFG,      
   --             DSSEN=>GND,      
   --             PSCLK=>GND,      
   --             PSEN=>GND,      
   --             PSINCDEC=>GND,      
   --             RST=>RST_IN,      
   --             CLKDV=>open,      
   --             CLKFX=>open,      
   --             CLKFX180=>open,      
   --             CLK0=>CLK0_BUF,      
   --             CLK2X=>open,      
   --             CLK2X180=>open,      
   --             CLK90=>open,      
   --             CLK180=>open,      
   --             CLK270=>open,      
   --             LOCKED=>LOCKED_OUT,      
   --             PSDONE=>open,      
   --             STATUS=>open);
  
 --Using the updated DCM_STANDBY component to handle new DCM constraints.
DCM_INST : dcm_standby 
   port map (
		CLKIN => CLKIN_IBUFG,
		CLKFB => CLKFB_IN,
		PSINCDEC =>GND ,
		PSEN => GND,
		PSCLK =>GND ,
		RST => RST_IN,
		CLK0 =>CLK0_BUF,
		LOCKED => LOCKED_OUT
		); 
  
  
end BEHAVIORAL;