📄 c8051f500.inc
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CAN0IF1M2L DATA 0C6H ; IF1 Mask 2 Low Byte
CAN0IF1M2H DATA 0C7H ; IF1 Mask 2 High Byte
CAN0IF1A1L DATA 0CAH ; IF1 Arbitration 1 Low Byte
CAN0IF1A1H DATA 0CBH ; IF1 Arbitration 1 High Byte
CAN0IF1A2L DATA 0CCH ; IF1 Arbitration 2 Low Byte
CAN0IF1A2H DATA 0CDH ; IF1 Arbitration 2 High Byte
CAN0IF2MCL DATA 0CEH ; IF2 Message Control Low Byte
CAN0IF2MCH DATA 0CFH ; IF2 Message Control High Byte
CAN0IF1MCL DATA 0D2H ; IF1 Message Control Low Byte
CAN0IF1MCH DATA 0D3H ; IF1 Message Control High Byte
CAN0IF1DA1L DATA 0D4H ; IF1 Data A 1 Low Byte
CAN0IF1DA1H DATA 0D5H ; IF1 Data A 1 High Byte
CAN0IF1DA2L DATA 0D6H ; IF1 Data A 2 Low Byte
CAN0IF1DA2H DATA 0D7H ; IF1 Data A 2 High Byte
CAN0IF1DB1L DATA 0DAH ; IF1 Data B 1 Low Byte
CAN0IF1DB1H DATA 0DBH ; IF1 Data B 1 High Byte
CAN0IF1DB2L DATA 0DCH ; IF1 Data B 2 Low Byte
CAN0IF1DB2H DATA 0DDH ; IF1 Data B 2 High Byte
CAN0IF2CRL DATA 0DEH ; IF2 Command Request Low Byte
CAN0IF2CRH DATA 0DFH ; IF2 Command Request High Byte
CAN0IF2CML DATA 0E2H ; IF2 Command Mask Low Byte
CAN0IF2CMH DATA 0E3H ; IF2 Command Mask High Byte
CAN0IF2M1L DATA 0EAH ; IF2 Mask 1 Low Byte
CAN0IF2M1H DATA 0EBH ; IF2 Mask 1 High Byte
CAN0IF2M2L DATA 0ECH ; IF2 Mask 2 Low Byte
CAN0IF2M2H DATA 0EDH ; IF2 Mask 2 High Byte
CAN0IF2A1L DATA 0EEH ; IF2 Arbitration 1 Low Byte
CAN0IF2A1H DATA 0EFH ; IF2 Arbitration 1 High Byte
CAN0IF2A2L DATA 0F2H ; IF2 Arbitration 2 Low Byte
CAN0IF2A2H DATA 0F3H ; IF2 Arbitration 2 High Byte
CAN0IF2DA1L DATA 0F6H ; IF2 Data A 1 Low Byte
CAN0IF2DA1H DATA 0F7H ; IF2 Data A 1 High Byte
CAN0IF2DA2L DATA 0FAH ; IF2 Data A 2 Low Byte
CAN0IF2DA2H DATA 0FBH ; IF2 Data A 2 High Byte
CAN0IF2DB1L DATA 0FCH ; IF2 Data B 1 Low Byte
CAN0IF2DB1H DATA 0FDH ; IF2 Data B 1 High Byte
CAN0IF2DB2L DATA 0FEH ; IF2 Data B 2 Low Byte
CAN0IF2DB2H DATA 0FFH ; IF2 Data B 2 High Byte
;------------------------------------------------------------------------------
; LIN0 Indirect Registers
;------------------------------------------------------------------------------
#define LIN0DT1 0x00 ; LIN0 Data Byte 1
#define LIN0DT2 0x01 ; LIN0 Data Byte 2
#define LIN0DT3 0x02 ; LIN0 Data Byte 3
#define LIN0DT4 0x03 ; LIN0 Data Byte 4
#define LIN0DT5 0x04 ; LIN0 Data Byte 5
#define LIN0DT6 0x05 ; LIN0 Data Byte 6
#define LIN0DT7 0x06 ; LIN0 Data Byte 7
#define LIN0DT8 0x07 ; LIN0 Data Byte 8
#define LIN0CTRL 0x08 ; LIN0 Control
#define LIN0ST 0x09 ; LIN0 Status
#define LIN0ERR 0x0A ; LIN0 Error
#define LIN0SIZE 0x0B ; LIN0 Message Size
#define LIN0DIV 0x0C ; LIN0 Divider
#define LIN0MUL 0x0D ; LIN0 Multiplier
#define LIN0ID 0x0E ; LIN0 Identifier
;------------------------------------------------------------------------------
; Bit Definitions
;------------------------------------------------------------------------------
; TCON 0x88
TF1 BIT TCON.7 ; Timer 1 Overflow Flag
TR1 BIT TCON.6 ; Timer 1 On/Off Control
TF0 BIT TCON.5 ; Timer 0 Overflow Flag
TR0 BIT TCON.4 ; Timer 0 On/Off Control
IE1 BIT TCON.3 ; Ext. Interrupt 1 Edge Flag
IT1 BIT TCON.2 ; Ext. Interrupt 1 Type
IE0 BIT TCON.1 ; Ext. Interrupt 0 Edge Flag
IT0 BIT TCON.0 ; Ext. Interrupt 0 Type
; SCON0 0x98
S0MODE BIT SCON0.7 ; UART0 Mode 0
PERR0 BIT SCON0.6 ; UART0 Parity Error Flag
THRE0 BIT SCON0.5 ; UART0 Transmit Holding Reg. Empty
REN0 BIT SCON0.4 ; UART0 RX Enable
TBX0 BIT SCON0.3 ; UART0 TX Bit 8
RBX0 BIT SCON0.2 ; UART0 RX Bit 8
TI0 BIT SCON0.1 ; UART0 TX Interrupt Flag
RI0 BIT SCON0.0 ; UART0 RX Interrupt Flag
; IE 0xA8
EA BIT IE.7 ; Global Interrupt Enable
ESPI0 BIT IE.6 ; SPI0 Interrupt Enable
ET2 BIT IE.5 ; Timer 2 Interrupt Enable
ES0 BIT IE.4 ; UART0 Interrupt Enable
ET1 BIT IE.3 ; Timer 1 Interrupt Enable
EX1 BIT IE.2 ; External Interrupt 1 Enable
ET0 BIT IE.1 ; Timer 0 Interrupt Enable
EX0 BIT IE.0 ; External Interrupt 0 Enable
; IP 0xB8
; Bit 7 unused
PSPI0 BIT IP.6 ; SPI0 Interrupt Priority
PT2 BIT IP.5 ; Timer 2 Priority
PS0 BIT IP.4 ; UART0 Priority
PS BIT IP.4 ; UART0 Priority
PT1 BIT IP.3 ; Timer 1 Priority
PX1 BIT IP.2 ; External Interrupt 1 Priority
PT0 BIT IP.1 ; Timer 0 Priority
PX0 BIT IP.0 ; External Interrupt 0 Priority
; SMB0CN 0xC0
MASTER BIT SMB0CN.7 ; SMBus0 Master/Slave Indicator
TXMODE BIT SMB0CN.6 ; SMBus0 Transmit Mode Indicator
STA BIT SMB0CN.5 ; SMBus0 Start Flag
STO BIT SMB0CN.4 ; SMBus0 Stop Flag
ACKRQ BIT SMB0CN.3 ; SMBus0 Acknowledge Request
ARBLOST BIT SMB0CN.2 ; SMBus0 Arbitration Lost Indicator
ACK BIT SMB0CN.1 ; SMBus0 Acknowledge
SI BIT SMB0CN.0 ; SMBus0 Interrupt Flag
; TMR2CN 0xC8
TF2H BIT TMR2CN.7 ; Timer 2 High-Byte Overflow Flag
TF2L BIT TMR2CN.6 ; Timer 2 Low-Byte Overflow Flag
TF2LEN BIT TMR2CN.5 ; Timer 2 Low-Byte Flag Enable
TF2CEN BIT TMR2CN.4 ; Timer 2 Capture Enable
T2SPLIT BIT TMR2CN.3 ; Timer 2 Split-Mode Enable
TR2 BIT TMR2CN.2 ; Timer2 Run Enable
; Unused
T2XCLK BIT TMR2CN.0 ; Timer 2 Clk/8 Clock Source
; PSW 0xD0
CY BIT PSW.7 ; Carry Flag
AC BIT PSW.6 ; Auxiliary Carry Flag
F0 BIT PSW.5 ; User Flag 0
RS1 BIT PSW.4 ; Register Bank Select 1
RS0 BIT PSW.3 ; Register Bank Select 0
OV BIT PSW.2 ; Overflow Flag
F1 BIT PSW.1 ; User Flag 1
P BIT PSW.0 ; Accumulator Parity Flag
; PCA0CN 0xD8
CF BIT PCA0CN.7 ; PCA0 Counter Overflow Flag
CR BIT PCA0CN.6 ; PCA0 Counter Run Control Bit
CCF5 BIT PCA0CN.5 ; PCA0 Module 5 Interrupt Flag
CCF4 BIT PCA0CN.4 ; PCA0 Module 4 Interrupt Flag
CCF3 BIT PCA0CN.3 ; PCA0 Module 3 Interrupt Flag
CCF2 BIT PCA0CN.2 ; PCA0 Module 2 Interrupt Flag
CCF1 BIT PCA0CN.1 ; PCA0 Module 1 Interrupt Flag
CCF0 BIT PCA0CN.0 ; PCA0 Module 0 Interrupt Flag
; ADC0CN 0xE8
AD0EN BIT ADC0CN.7 ; ADC0 Enable
BURSTEN BIT ADC0CN.6 ; ADC0 Burst Enable
AD0INT BIT ADC0CN.5 ; ADC0 EOC Interrupt Flag
AD0BUSY BIT ADC0CN.4 ; ADC0 Busy Flag
AD0WINT BIT ADC0CN.3 ; ADC0 Window Compare Interrupt Flag
AD0LJST BIT ADC0CN.2 ; ADC0 Left Justified
AD0CM1 BIT ADC0CN.1 ; ADC0 Start Of Conversion Mode Bit 1
AD0CM0 BIT ADC0CN.0 ; ADC0 Start Of Conversion Mode Bit 0
; SPI0CN 0xF8
SPIF BIT SPI0CN.7 ; SPI0 Interrupt Flag
WCOL BIT SPI0CN.6 ; SPI0 Write Collision Flag
MODF BIT SPI0CN.5 ; SPI0 Mode Fault Flag
RXOVRN BIT SPI0CN.4 ; SPI0 RX Overrun Flag
NSSMD1 BIT SPI0CN.3 ; SPI0 Slave Select Mode 1
NSSMD0 BIT SPI0CN.2 ; SPI0 Slave Select Mode 0
TXBMT BIT SPI0CN.1 ; SPI0 TX Buffer Empty Flag
SPIEN BIT SPI0CN.0 ; SPI0 Enable
;-----------------------------------------------------------------------------
; Interrupt Priorities
;-----------------------------------------------------------------------------
#define INTERRUPT_INT0 0 ; External Interrupt 0
#define INTERRUPT_TIMER0 1 ; Timer0 Overflow
#define INTERRUPT_INT1 2 ; External Interrupt 1
#define INTERRUPT_TIMER1 3 ; Timer1 Overflow
#define INTERRUPT_UART0 4 ; UART0
#define INTERRUPT_TIMER2 5 ; Timer2 Overflow
#define INTERRUPT_SPI0 6 ; SPI0
#define INTERRUPT_SMBUS0 7 ; SMBus0 Interface
#define INTERRUPT_ADC0_WINDOW 8 ; ADC0 Window Comparison
#define INTERRUPT_ADC0_EOC 9 ; ADC0 End Of Conversion
#define INTERRUPT_PCA0 10 ; PCA0 Peripheral
#define INTERRUPT_COMPARATOR0 11 ; Comparator0 Comparison
#define INTERRUPT_COMPARATOR1 12 ; Comparator1 Comparison
#define INTERRUPT_TIMER3 13 ; Timer3 Overflow
#define INTERRUPT_LIN0 14 ; LIN Bus Interrupt
#define INTERRUPT_VREG 15 ; Voltage Regulator
#define INTERRUPT_CAN0 16 ; CAN Bus Interrupt
#define INTERRUPT_PORT_MATCH 17 ; Port Match
;------------------------------------------------------------------------------
; SFR Page Definitions
;------------------------------------------------------------------------------
#define CONFIG_PAGE 0x0F ; System and Port Configuration Page
#define ACTIVE_PAGE 0x00 ; Active Use Page
#define CAN0_PAGE 0x0C ; CAN0 Registers
;------------------------------------------------------------------------------
; End Of File
;------------------------------------------------------------------------------⌨️ 快捷键说明
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