📄 c8051f500.inc
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;------------------------------------------------------------------------------
; C8051F500.INC
;------------------------------------------------------------------------------
; Copyright 2008, Silicon Laboratories, Inc.
; http://www.silabs.com
;
; Program Description:
;
; Register/bit definitions for the C8051F50x family.
;
; Target: C8051F500/1/2/3/4/5/6/7
; Tool chain: Keil
; Command Line: None
;
; Release 0.6 - 17 JUL 2008 (GP)
; -Fixed SCON0 and TMR2CN bit definitions
;
; Release 0.5 - 09 JUL 2008 (GP)
; -Initial release
;------------------------------------------------------------------------------
; Page 0 and Page F Registers
;------------------------------------------------------------------------------
P0 DATA 080H ; Port 0 Latch
SP DATA 081H ; Stack Pointer
DPL DATA 082H ; Data Pointer Low
DPH DATA 083H ; Data Pointer High
SFR0CN DATA 084H ; SFR Page Control
SFRNEXT DATA 085H ; SFR stack next page
SFRLAST DATA 086H ; SFR stack last page
PCON DATA 087H ; Power Control
TCON DATA 088H ; Timer/Counter Control
TMOD DATA 089H ; Timer/Counter Mode
TL0 DATA 08AH ; Timer/Counter 0 Low
TL1 DATA 08BH ; Timer/Counter 1 Low
TH0 DATA 08CH ; Timer/Counter 0 High
TH1 DATA 08DH ; Timer/Counter 1 High
CKCON DATA 08EH ; Clock Control
PSCTL DATA 08FH ; Program Store R/W Control
CLKSEL DATA 08FH ; System clock select
P1 DATA 090H ; Port 1 Latch
TMR3CN DATA 091H ; Timer/Counter 3 Control
TMR3RLL DATA 092H ; Timer/Counter 3 Reload Low
TMR3RLH DATA 093H ; Timer/Counter 3 Reload High
TMR3L DATA 094H ; Timer/Counter 3 Low
TMR3H DATA 095H ; Timer/Counter 3 High
CLKMUL DATA 097H ; Clock Multiplier
SCON0 DATA 098H ; UART0 Control
SBUF0 DATA 099H ; UART0 Data Buffer
CPT0CN DATA 09AH ; Comparator 0 Control
CPT0MD DATA 09BH ; Comparator 0 Mode
CPT0MX DATA 09CH ; Comparator 0 Mux
CPT1CN DATA 09DH ; Comparator 1 Control
CPT1MD DATA 09EH ; Comparator 0 Mode
OSCIFIN DATA 09EH ; Internal Oscillator Fine Control
CPT1MX DATA 09FH ; Comparator 1 Mux
OSCXCN DATA 09FH ; External Oscillator Control
P2 DATA 0A0H ; Port 2 Latch
SPI0CFG DATA 0A1H ; SPI0 Configuration
OSCICN DATA 0A1H ; Internal Oscillator Control
SPI0CKR DATA 0A2H ; SPI0 Clock rate control
OSCICRS DATA 0A2H ; Internal Oscillator Coarse Control
SPI0DAT DATA 0A3H ; SPI0 Data Buffer
P0MDOUT DATA 0A4H ; Port 0 Output Mode
P1MDOUT DATA 0A5H ; Port 1 Output Mode
P2MDOUT DATA 0A6H ; Port 2 Output Mode
SFRPAGE DATA 0A7H ; SFR Page Select
IE DATA 0A8H ; Interrupt Enable
SMOD0 DATA 0A9H ; Serial Port 0 Control
EMI0CN DATA 0AAH ; EMIF control
EMI0TC DATA 0AAH ; EMIF Timing control
SBCON0 DATA 0ABH ; UART0 Baud Rate Generator Control
SBRLL0 DATA 0ACH ; UART0 Baud Rate Generator Low
SBRLH0 DATA 0ADH ; UART0 Baud Rate Generator High
P3MAT DATA 0AEH ; Port 3 Match
P3MDOUT DATA 0AEH ; Port 3 Mode
P3MASK DATA 0AFH ; Port 3 Mask
P4MDOUT DATA 0AFH ; Port 4 Mode
P3 DATA 0B0H ; Port 3 Latch
P2MAT DATA 0B1H ; Port 2 Match
P2MASK DATA 0B2H ; Port 2 Mask
EMI0CF DATA 0B2H ; EMIF Configuration
P4 DATA 0B5H ; Port 4 Latch
FLSCL DATA 0B6H ; Flash Scale
FLKEY DATA 0B7H ; Flash access limit
IP DATA 0B8H ; Interrupt Priority
SMB0ADR DATA 0B9H ; SMBus0 Slave address
ADC0TK DATA 0BAH ; ADC0 Tracking Select
SMB0ADM DATA 0BAH ; SMBus0 Address Mask
ADC0MX DATA 0BBH ; AMUX0 Channel select
ADC0CF DATA 0BCH ; AMUX0 Channel configuration
ADC0L DATA 0BDH ; ADC0 Data Low
ADC0H DATA 0BEH ; ADC0 Data High
SMB0CN DATA 0C0H ; SMBus0 Control
SMB0CF DATA 0C1H ; SMBus0 Configuration
SMB0DAT DATA 0C2H ; SMBus0 Data
ADC0GTL DATA 0C3H ; ADC0 Greater-Than Compare Low
ADC0GTH DATA 0C4H ; ADC0 Greater-Than Compare High
ADC0LTL DATA 0C5H ; ADC0 Less-Than Compare Word Low
ADC0LTH DATA 0C6H ; ADC0 Less-Than Compare Word High
XBR2 DATA 0C7H ; Port I/O Crossbar Control 2
TMR2CN DATA 0C8H ; Timer/Counter 2 Control
REG0CN DATA 0C9H ; Regulator Control
LIN0CF DATA 0C9H ; LIN 0 Configuration
TMR2RLL DATA 0CAH ; Timer/Counter 2 Reload Low
TMR2RLH DATA 0CBH ; Timer/Counter 2 Reload High
TMR2L DATA 0CCH ; Timer/Counter 2 Low
TMR2H DATA 0CDH ; Timer/Counter 2 High
PCA0CPL5 DATA 0CEH ; PCA0 Capture 5 Low
PCA0CPH5 DATA 0CFH ; PCA0 Capture 5 High
PSW DATA 0D0H ; Program Status Word
REF0CN DATA 0D1H ; Voltage Reference Control
LIN0DAT DATA 0D2H ; LIN0 Data
LIN0ADR DATA 0D3H ; LIN0 Address
P0SKIP DATA 0D4H ; Port 0 Skip
P1SKIP DATA 0D5H ; Port 1 Skip
P2SKIP DATA 0D6H ; Port 2 Skip
P3SKIP DATA 0D7H ; Port 3 Skip
PCA0CN DATA 0D8H ; PCA0 Control
PCA0MD DATA 0D9H ; PCA0 Mode
PCA0PWM DATA 0D9H ; PCA0 PWM Control
PCA0CPM0 DATA 0DAH ; PCA0 Module 0 Mode Register
PCA0CPM1 DATA 0DBH ; PCA0 Module 1 Mode Register
PCA0CPM2 DATA 0DCH ; PCA0 Module 2 Mode Register
PCA0CPM3 DATA 0DDH ; PCA0 Module 3 Mode Register
PCA0CPM4 DATA 0DEH ; PCA0 Module 4 Mode Register
PCA0CPM5 DATA 0DFH ; PCA0 Module 5 Mode Register
ACC DATA 0E0H ; Accumulator
XBR0 DATA 0E1H ; Port I/O Crossbar Control 0
XBR1 DATA 0E2H ; Port I/O Crossbar Control 1
CCH0CN DATA 0E3H ; Cache control
IT01CF DATA 0E4H ; INT0/INT1 Configuration
EIE1 DATA 0E6H ; Extended Interrupt Enable 2
EIE2 DATA 0E7H ; Extended Interrupt Enable 2
ADC0CN DATA 0E8H ; ADC0 Control
PCA0CPL1 DATA 0E9H ; PCA0 Capture 2 Low
PCA0CPH1 DATA 0EAH ; PCA0 Capture 2 High
PCA0CPL2 DATA 0EBH ; PCA0 Capture 3 Low
PCA0CPH2 DATA 0ECH ; PCA0 Capture 3 High
PCA0CPL3 DATA 0EDH ; PCA0 Capture 4 Low
PCA0CPH3 DATA 0EEH ; PCA0 Capture 4 High
RSTSRC DATA 0EFH ; Reset Source Configuration/Status
B DATA 0F0H ; B Register
P0MAT DATA 0F1H ; Port 0 Match
P0MDIN DATA 0F1H ; Port 0 Input Mode
P0MASK DATA 0F2H ; Port 0 Mask
P1MDIN DATA 0F2H ; Port 1 Input Mode
P1MAT DATA 0F3H ; Port 1 Match
P2MDIN DATA 0F3H ; Port 2 Input Mode
P1MASK DATA 0F4H ; Port 1 Mask
P3MDIN DATA 0F4H ; Port 3 Input Mode
EIP1 DATA 0F6H ; External Interrupt Priority 1
EIP2 DATA 0F7H ; External Interrupt Priority 2
SPI0CN DATA 0F8H ; SPI0 Control
PCA0L DATA 0F9H ; PCA0 Counter Low
PCA0H DATA 0FAH ; PCA0 Counter High
PCA0CPL0 DATA 0FBH ; PCA0 Capture 0 Low
PCA0CPH0 DATA 0FCH ; PCA0 Capture 0 High
PCA0CPL4 DATA 0FDH ; PCA0 Capture 4 Low
PCA0CPH4 DATA 0FEH ; PCA0 Capture 4 High
VDM0CN DATA 0FFH ; VDD Monitor Control
;------------------------------------------------------------------------------
; Page C (CAN0) Registers
;------------------------------------------------------------------------------
CAN0CFG DATA 092H ; CAN0 Clock Configuration
CAN0STAT DATA 094H ; Status Register Low Byte
CAN0ERRL DATA 096H ; Error Counter Low Byte
CAN0ERRH DATA 097H ; Error Counter High Byte
CAN0BTL DATA 09AH ; Bit Timing Register Low Byte
CAN0BTH DATA 09BH ; Bit Timing Register High Byte
CAN0IIDL DATA 09CH ; Interrupt Register Low Byte
CAN0IIDH DATA 09DH ; Interrupt Register High Byte
CAN0TST DATA 09EH ; Test Register Low Byte
CAN0BRPE DATA 0A1H ; BRP Extension Register Low Byte
CAN0TR1L DATA 0A2H ; Transmission Request 1 Low Byte
CAN0TR1H DATA 0A3H ; Transmission Request 1 High Byte
CAN0TR2L DATA 0A4H ; Transmission Request 2 Low Byte
CAN0TR2H DATA 0A5H ; Transmission Request 2 High Byte
CAN0ND1L DATA 0AAH ; New Data 1 Low Byte
CAN0ND1H DATA 0ABH ; New Data 1 High Byte
CAN0ND2L DATA 0ACH ; New Data 2 Low Byte
CAN0ND2H DATA 0ADH ; New Data 2 High Byte
CAN0IP1L DATA 0AEH ; Interrupt Pending 1 Low Byte
CAN0IP1H DATA 0AFH ; Interrupt Pending 1 High Byte
CAN0IP2L DATA 0B2H ; Interrupt Pending 2 Low Byte
CAN0IP2H DATA 0B3H ; Interrupt Pending 2 High Byte
CAN0MV1L DATA 0BAH ; Message Valid 1 Low Byte
CAN0MV1H DATA 0BBH ; Message Valid 1 High Byte
CAN0MV2L DATA 0BCH ; Message Valid 2 Low Byte
CAN0MV2H DATA 0BDH ; Message Valid 2 High Byte
CAN0IF1CRL DATA 0BEH ; IF1 Command Request Low Byte
CAN0IF1CRH DATA 0BFH ; IF1 Command Request High Byte
CAN0CN DATA 0C0H ; CAN Control Register Low Byte
CAN0IF1CML DATA 0C2H ; IF1 Command Mask Low Byte
CAN0IF1CMH DATA 0C3H ; IF1 Command Mask High Byte
CAN0IF1M1L DATA 0C4H ; IF1 Mask 1 Low Byte
CAN0IF1M1H DATA 0C5H ; IF1 Mask 1 High Byte
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