c8051f500_defs.h

C8051F500开发编程：MCU全部资源应用实例

//-----------------------------------------------------------------------------
// C8051F500_defs.h
//-----------------------------------------------------------------------------
// Copyright 2008, Silicon Laboratories, Inc.
// http://www.silabs.com
//
// Program Description:
//
// Register/bit definitions for the C8051F50x family.
// **Important Note**: The compiler_defs.h header file should be included
// before including this header file.
//
// Target:         C8051F500/1/2/3/4/5/6/7
// Tool chain:     Generic
// Command Line:   None
//
// Release 0.4 - 17 JUL 2008 (GP)
//    -Fixed SCON0 and TMR2CN bit defintions
//
// Release 0.3 - 09 JUL 2008 (GP)
//    -Initial release
//

//-----------------------------------------------------------------------------
// Header File Preprocessor Directive
//-----------------------------------------------------------------------------

#ifndef C8051F500_DEFS_H
#define C8051F500_DEFS_H

//-----------------------------------------------------------------------------
// Page 0 and Page F Registers
//-----------------------------------------------------------------------------

SFR (P0, 0x80);                        // Port 0 Latch
SFR (SP, 0x81);                        // Stack Pointer
SFR (DPL, 0x82);                       // Data Pointer Low
SFR (DPH, 0x83);                       // Data Pointer High
SFR (SFR0CN, 0x84);                    // SFR Page Control
SFR (SFRNEXT, 0x85);                   // SFR stack next page
SFR (SFRLAST, 0x86);                   // SFR stack last page
SFR (PCON, 0x87);                      // Power Control
SFR (TCON, 0x88);                      // Timer/Counter Control
SFR (TMOD, 0x89);                      // Timer/Counter Mode
SFR (TL0, 0x8A);                       // Timer/Counter 0 Low
SFR (TL1, 0x8B);                       // Timer/Counter 1 Low
SFR (TH0, 0x8C);                       // Timer/Counter 0 High
SFR (TH1, 0x8D);                       // Timer/Counter 1 High
SFR (CKCON, 0x8E);                     // Clock Control
SFR (PSCTL, 0x8F);                     // Program Store R/W Control
SFR (CLKSEL, 0x8F);                    // System clock select
SFR (P1, 0x90);                        // Port 1 Latch
SFR (TMR3CN, 0x91);                    // Timer/Counter 3 Control
SFR (TMR3RLL, 0x92);                   // Timer/Counter 3 Reload Low
SFR (TMR3RLH, 0x93);                   // Timer/Counter 3 Reload High
SFR (TMR3L, 0x94);                     // Timer/Counter 3 Low
SFR (TMR3H, 0x95);                     // Timer/Counter 3 High
SFR (CLKMUL, 0x97);                    // Clock Multiplier
SFR (SCON0, 0x98);                     // UART0 Control
SFR (SBUF0, 0x99);                     // UART0 Data Buffer
SFR (CPT0CN, 0x9A);                    // Comparator 0 Control
SFR (CPT0MD, 0x9B);                    // Comparator 0 Mode
SFR (CPT0MX, 0x9C);                    // Comparator 0 Mux
SFR (CPT1CN, 0x9D);                    // Comparator 1 Control
SFR (CPT1MD, 0x9E);                    // Comparator 0 Mode
SFR (OSCIFIN, 0x9E);                   // Internal Oscillator Fine Control
SFR (CPT1MX, 0x9F);                    // Comparator 1 Mux
SFR (OSCXCN, 0x9F);                    // External Oscillator Control
SFR (P2, 0xA0);                        // Port 2 Latch
SFR (SPI0CFG, 0xA1);                   // SPI0 Configuration
SFR (OSCICN, 0xA1);                    // Internal Oscillator Control
SFR (SPI0CKR, 0xA2);                   // SPI0 Clock rate control
SFR (OSCICRS, 0xA2);                   // Internal Oscillator Coarse Control
SFR (SPI0DAT, 0xA3);                   // SPI0 Data Buffer
SFR (P0MDOUT, 0xA4);                   // Port 0 Output Mode
SFR (P1MDOUT, 0xA5);                   // Port 1 Output Mode
SFR (P2MDOUT, 0xA6);                   // Port 2 Output Mode
SFR (SFRPAGE, 0xA7);                   // SFR Page Select
SFR (IE, 0xA8);                        // Interrupt Enable
SFR (SMOD0, 0xA9);                     // Serial Port 0 Control
SFR (EMI0CN, 0xAA);                    // EMIF control
SFR (EMI0TC, 0xAA);                    // EMIF Timing control
SFR (SBCON0, 0xAB);                    // UART0 Baud Rate Generator Control
SFR (SBRLL0, 0xAC);                    // UART0 Baud Rate Generator Low
SFR (SBRLH0, 0xAD);                    // UART0 Baud Rate Generator High
SFR (P3MAT, 0xAE);                     // Port 3 Match
SFR (P3MDOUT, 0xAE);                   // Port 3 Mode
SFR (P3MASK, 0xAF);                    // Port 3 Mask
SFR (P4MDOUT, 0xAF);                   // Port 4 Mode
SFR (P3, 0xB0);                        // Port 3 Latch
SFR (P2MAT, 0xB1);                     // Port 2 Match
SFR (P2MASK, 0xB2);                    // Port 2 Mask
SFR (EMI0CF, 0xB2);                    // EMIF Configuration
SFR (P4, 0xB5);                        // Port 4 Latch
SFR (FLSCL, 0xB6);                     // Flash Scale
SFR (FLKEY, 0xB7);                     // Flash access limit
SFR (IP, 0xB8);                        // Interrupt Priority
SFR (SMB0ADR, 0xB9);                   // SMBus0 Slave address
SFR (ADC0TK, 0xBA);                    // ADC0 Tracking Mode Select
SFR (SMB0ADM, 0xBA);                   // SMBus0 Address Mask
SFR (ADC0MX, 0xBB);                    // AMUX0 Channel select
SFR (ADC0CF, 0xBC);                    // AMUX0 Channel configuration
SFR (ADC0L, 0xBD);                     // ADC0 Data Low
SFR (ADC0H, 0xBE);                     // ADC0 Data High
SFR (SMB0CN, 0xC0);                    // SMBus0 Control
SFR (SMB0CF, 0xC1);                    // SMBus0 Configuration
SFR (SMB0DAT, 0xC2);                   // SMBus0 Data
SFR (ADC0GTL, 0xC3);                   // ADC0 Greater-Than Compare Low
SFR (ADC0GTH, 0xC4);                   // ADC0 Greater-Than Compare High
SFR (ADC0LTL, 0xC5);                   // ADC0 Less-Than Compare Word Low
SFR (ADC0LTH, 0xC6);                   // ADC0 Less-Than Compare Word High
SFR (XBR2, 0xC7);                      // Port I/O Crossbar Control 2
SFR (TMR2CN, 0xC8);                    // Timer/Counter 2 Control
SFR (REG0CN, 0xC9);                    // Regulator Control
SFR (LIN0CF, 0xC9);                    // LIN 0 Configuration
SFR (TMR2RLL, 0xCA);                   // Timer/Counter 2 Reload Low
SFR (TMR2RLH, 0xCB);                   // Timer/Counter 2 Reload High
SFR (TMR2L, 0xCC);                     // Timer/Counter 2 Low
SFR (TMR2H, 0xCD);                     // Timer/Counter 2 High
SFR (PCA0CPL5, 0xCE);                  // PCA0 Capture 5 Low
SFR (PCA0CPH5, 0xCF);                  // PCA0 Capture 5 High
SFR (PSW, 0xD0);                       // Program Status Word
SFR (REF0CN, 0xD1);                    // Voltage Reference Control
SFR (LIN0DAT, 0xD2);                   // LIN0 Data
SFR (LIN0ADR, 0xD3);                   // LIN0 Address
SFR (P0SKIP, 0xD4);                    // Port 0 Skip
SFR (P1SKIP, 0xD5);                    // Port 1 Skip
SFR (P2SKIP, 0xD6);                    // Port 2 Skip
SFR (P3SKIP, 0xD7);                    // Port 3 Skip
SFR (PCA0CN, 0xD8);                    // PCA0 Control
SFR (PCA0MD, 0xD9);                    // PCA0 Mode
SFR (PCA0PWM, 0xD9);                   // PCA0 PWM Control
SFR (PCA0CPM0, 0xDA);                  // PCA0 Module 0 Mode Register
SFR (PCA0CPM1, 0xDB);                  // PCA0 Module 1 Mode Register
SFR (PCA0CPM2, 0xDC);                  // PCA0 Module 2 Mode Register
SFR (PCA0CPM3, 0xDD);                  // PCA0 Module 3 Mode Register
SFR (PCA0CPM4, 0xDE);                  // PCA0 Module 4 Mode Register
SFR (PCA0CPM5, 0xDF);                  // PCA0 Module 5 Mode Register
SFR (ACC, 0xE0);                       // Accumulator
SFR (XBR0, 0xE1);                      // Port I/O Crossbar Control 0
SFR (XBR1, 0xE2);                      // Port I/O Crossbar Control 1
SFR (CCH0CN, 0xE3);                    // Cache control
SFR (IT01CF, 0xE4);                    // INT0/INT1 Configuration
SFR (EIE1, 0xE6);                      // Extended Interrupt Enable 2
SFR (EIE2, 0xE7);                      // Extended Interrupt Enable 2
SFR (ADC0CN, 0xE8);                    // ADC0 Control
SFR (PCA0CPL1, 0xE9);                  // PCA0 Capture 2 Low
SFR (PCA0CPH1, 0xEA);                  // PCA0 Capture 2 High
SFR (PCA0CPL2, 0xEB);                  // PCA0 Capture 3 Low
SFR (PCA0CPH2, 0xEC);                  // PCA0 Capture 3 High
SFR (PCA0CPL3, 0xED);                  // PCA0 Capture 4 Low
SFR (PCA0CPH3, 0xEE);                  // PCA0 Capture 4 High
SFR (RSTSRC, 0xEF);                    // Reset Source Configuration/Status
SFR (B, 0xF0);                         // B Register
SFR (P0MAT, 0xF1);                     // Port 0 Match
SFR (P0MDIN, 0xF1);                    // Port 0 Input Mode
SFR (P0MASK, 0xF2);                    // Port 0 Mask
SFR (P1MDIN, 0xF2);                    // Port 1 Input Mode
SFR (P1MAT, 0xF3);                     // Port 1 Match
SFR (P2MDIN, 0xF3);                    // Port 2 Input Mode
SFR (P1MASK, 0xF4);                    // Port 1 Mask
SFR (P3MDIN, 0xF4);                    // Port 3 Input Mode
SFR (EIP1, 0xF6);                      // External Interrupt Priority 1
SFR (EIP2, 0xF7);                      // External Interrupt Priority 2
SFR (SPI0CN, 0xF8);                    // SPI0 Control
SFR (PCA0L, 0xF9);                     // PCA0 Counter Low
SFR (PCA0H, 0xFA);                     // PCA0 Counter High
SFR (PCA0CPL0, 0xFB);                  // PCA0 Capture 0 Low
SFR (PCA0CPH0, 0xFC);                  // PCA0 Capture 0 High
SFR (PCA0CPL4, 0xFD);                  // PCA0 Capture 4 Low
SFR (PCA0CPH4, 0xFE);                  // PCA0 Capture 4 High
SFR (VDM0CN, 0xFF);                    // VDD Monitor Control

//-----------------------------------------------------------------------------
// Page C (CAN0) Registers
//-----------------------------------------------------------------------------

SFR (CAN0CFG, 0x92);                   // CAN0 Clock Configuration
SFR (CAN0STAT, 0x94);                  // Status Register Low Byte
SFR (CAN0ERRL, 0x96);                  // Error Counter Low Byte
SFR (CAN0ERRH, 0x97);                  // Error Counter High Byte
SFR (CAN0BTL, 0x9A);                   // Bit Timing Register Low Byte
SFR (CAN0BTH, 0x9B);                   // Bit Timing Register High Byte
SFR (CAN0IIDL, 0x9C);                  // Interrupt Register Low Byte
SFR (CAN0IIDH, 0x9D);                  // Interrupt Register High Byte
SFR (CAN0TST, 0x9E);                   // Test Register Low Byte
SFR (CAN0BRPE, 0xA1);                  // BRP Extension Register Low Byte
SFR (CAN0TR1L, 0xA2);                  // Transmission Request 1 Low Byte
SFR (CAN0TR1H, 0xA3);                  // Transmission Request 1 High Byte
SFR (CAN0TR2L, 0xA4);                  // Transmission Request 2 Low Byte
SFR (CAN0TR2H, 0xA5);                  // Transmission Request 2 High Byte
SFR (CAN0ND1L, 0xAA);                  // New Data 1 Low Byte
SFR (CAN0ND1H, 0xAB);                  // New Data 1 High Byte
SFR (CAN0ND2L, 0xAC);                  // New Data 2 Low Byte
SFR (CAN0ND2H, 0xAD);                  // New Data 2 High Byte
SFR (CAN0IP1L, 0xAE);                  // Interrupt Pending 1 Low Byte
SFR (CAN0IP1H, 0xAF);                  // Interrupt Pending 1 High Byte
SFR (CAN0IP2L, 0xB2);                  // Interrupt Pending 2 Low Byte
SFR (CAN0IP2H, 0xB3);                  // Interrupt Pending 2 High Byte
SFR (CAN0MV1L, 0xBA);                  // Message Valid 1 Low Byte
SFR (CAN0MV1H, 0xBB);                  // Message Valid 1 High Byte
SFR (CAN0MV2L, 0xBC);                  // Message Valid 2 Low Byte
SFR (CAN0MV2H, 0xBD);                  // Message Valid 2 High Byte
SFR (CAN0IF1CRL, 0xBE);                // IF1 Command Request Low Byte
SFR (CAN0IF1CRH, 0xBF);                // IF1 Command Request High Byte
SFR (CAN0CN, 0xC0);                    // CAN Control Register Low Byte
SFR (CAN0IF1CML, 0xC2);                // IF1 Command Mask Low Byte
SFR (CAN0IF1CMH, 0xC3);                // IF1 Command Mask High Byte
SFR (CAN0IF1M1L, 0xC4);                // IF1 Mask 1 Low Byte
SFR (CAN0IF1M1H, 0xC5);                // IF1 Mask 1 High Byte
SFR (CAN0IF1M2L, 0xC6);                // IF1 Mask 2 Low Byte
SFR (CAN0IF1M2H, 0xC7);                // IF1 Mask 2 High Byte
SFR (CAN0IF1A1L, 0xCA);                // IF1 Arbitration 1 Low Byte
SFR (CAN0IF1A1H, 0xCB);                // IF1 Arbitration 1 High Byte
SFR (CAN0IF1A2L, 0xCC);                // IF1 Arbitration 2 Low Byte
SFR (CAN0IF1A2H, 0xCD);                // IF1 Arbitration 2 High Byte
SFR (CAN0IF2MCL, 0xCE);                // IF2 Message Control Low Byte
SFR (CAN0IF2MCH, 0xCF);                // IF2 Message Control High Byte
SFR (CAN0IF1MCL, 0xD2);                // IF1 Message Control Low Byte
SFR (CAN0IF1MCH, 0xD3);                // IF1 Message Control High Byte
SFR (CAN0IF1DA1L, 0xD4);               // IF1 Data A 1 Low Byte
SFR (CAN0IF1DA1H, 0xD5);               // IF1 Data A 1 High Byte
SFR (CAN0IF1DA2L, 0xD6);               // IF1 Data A 2 Low Byte
SFR (CAN0IF1DA2H, 0xD7);               // IF1 Data A 2 High Byte
SFR (CAN0IF1DB1L, 0xDA);               // IF1 Data B 1 Low Byte
SFR (CAN0IF1DB1H, 0xDB);               // IF1 Data B 1 High Byte
SFR (CAN0IF1DB2L, 0xDC);               // IF1 Data B 2 Low Byte
SFR (CAN0IF1DB2H, 0xDD);               // IF1 Data B 2 High Byte
SFR (CAN0IF2CRL, 0xDE);                // IF2 Command Request Low Byte
SFR (CAN0IF2CRH, 0xDF);                // IF2 Command Request High Byte
SFR (CAN0IF2CML, 0xE2);                // IF2 Command Mask Low Byte
SFR (CAN0IF2CMH, 0xE3);                // IF2 Command Mask High Byte
SFR (CAN0IF2M1L, 0xEA);                // IF2 Mask 1 Low Byte
SFR (CAN0IF2M1H, 0xEB);                // IF2 Mask 1 High Byte
SFR (CAN0IF2M2L, 0xEC);                // IF2 Mask 2 Low Byte
SFR (CAN0IF2M2H, 0xED);                // IF2 Mask 2 High Byte
SFR (CAN0IF2A1L, 0xEE);                // IF2 Arbitration 1 Low Byte
SFR (CAN0IF2A1H, 0xEF);                // IF2 Arbitration 1 High Byte
SFR (CAN0IF2A2L, 0xF2);                // IF2 Arbitration 2 Low Byte
SFR (CAN0IF2A2H, 0xF3);                // IF2 Arbitration 2 High Byte
SFR (CAN0IF2DA1L, 0xF6);               // IF2 Data A 1 Low Byte
SFR (CAN0IF2DA1H, 0xF7);               // IF2 Data A 1 High Byte
SFR (CAN0IF2DA2L, 0xFA);               // IF2 Data A 2 Low Byte
SFR (CAN0IF2DA2H, 0xFB);               // IF2 Data A 2 High Byte
SFR (CAN0IF2DB1L, 0xFC);               // IF2 Data B 1 Low Byte
SFR (CAN0IF2DB1H, 0xFD);               // IF2 Data B 1 High Byte