sin_cos.vhd

Sin & Cos generator (one from DSP steps)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library altera_mf;
use altera_mf.all;

entity sin_cos is 
    port(
        clk                 : in std_logic;
        phi                 : in std_logic_vector(14 downto 0);
        Dien                : in std_logic;
        cos                 : out std_logic_vector(15 downto 0);
        sin                 : out std_logic_vector(15 downto 0);
        Doen                : out std_logic
        );
end sin_cos;


architecture sin_cos_arch of sin_cos is    
    
    component altsyncram
        generic (
            address_reg_b		                : string;
            clock_enable_input_a		        : string;
            clock_enable_input_b		        : string;
            clock_enable_output_a		        : string;
            clock_enable_output_b		        : string;
            indata_reg_b		                : string;
            init_file		                    : string;
            intended_device_family		        : string;
            lpm_type		                    : string;
            numwords_a		                    : natural;
            numwords_b		                    : natural;
            operation_mode		                : string;
            outdata_aclr_a		                : string;
            outdata_aclr_b		                : string;
            outdata_reg_a		                : string;
            outdata_reg_b		                : string;
            power_up_uninitialized		        : string;
            read_during_write_mode_mixed_ports	: string;
            read_during_write_mode_port_a		: string;
            read_during_write_mode_port_b		: string;
            widthad_a		                    : natural;
            widthad_b		                    : natural;
            width_a		                        : natural;
            width_b		                        : natural;
            width_byteena_a		                : natural;
            width_byteena_b		                : natural;
            wrcontrol_wraddress_reg_b		    : string
            );
        port (
            clock0                              : in std_logic; 
            wren_a	                            : in std_logic;
            address_a	                        : in std_logic_vector (12 downto 0);
            data_a	                            : in std_logic_vector (15 downto 0);
            q_a	                                : out std_logic_vector (15 downto 0); 
            wren_b	                            : in std_logic;
            address_b	                        : in std_logic_vector (12 downto 0);
            data_b	                            : in std_logic_vector (15 downto 0);
            q_b	                                : out std_logic_vector (15 downto 0)
            );
    end component;   
    
    constant PI_POS                             : unsigned (14 downto 0) := "100" & X"000";
    
    signal sin_addr, cos_addr                   : std_logic_vector (12 downto 0);
    signal sin_data, cos_data                   : std_logic_vector (15 downto 0); 
    signal negs, q_negs, qq_negs, qqq_negs      : std_logic;
    signal negc, q_negc, qq_negc, qqq_negc      : std_logic;
    signal neg_cos, q_neg_cos                   : std_logic;
    signal q_Dien, qq_Dien, qqq_Dien            : std_logic;
    
begin  
    
    table: altsyncram
    generic map (
        address_reg_b                           => "CLOCK0",
        clock_enable_input_a                    => "BYPASS",
        clock_enable_input_b                    => "BYPASS",
        clock_enable_output_a                   => "BYPASS",
        clock_enable_output_b                   => "BYPASS",
        indata_reg_b                            => "CLOCK0",
        init_file                               => "sin_table.mif",
        intended_device_family                  => "Cyclone III",
        lpm_type                                => "altsyncram",
        numwords_a                              => 8192,
        numwords_b                              => 8192,
        operation_mode                          => "BIDIR_DUAL_PORT",
        outdata_aclr_a                          => "NONE",
        outdata_aclr_b                          => "NONE",
        outdata_reg_a                           => "CLOCK0",
        outdata_reg_b                           => "CLOCK0",
        power_up_uninitialized                  => "FALSE",
        read_during_write_mode_mixed_ports      => "DONT_CARE",
        read_during_write_mode_port_a           => "NEW_DATA_NO_NBE_READ",
        read_during_write_mode_port_b           => "NEW_DATA_NO_NBE_READ",
        widthad_a                               => 13,
        widthad_b                               => 13,
        width_a                                 => 16,
        width_b                                 => 16,
        width_byteena_a                         => 1,
        width_byteena_b                         => 1,
        wrcontrol_wraddress_reg_b               => "CLOCK0"
        )                                       
    port map (                                  
        clock0                                  => clk,
        address_a                               => std_logic_vector(sin_addr),
        data_a                                  => (others =>'0'),
        wren_a                                  => '0',
        q_a                                     => sin_data,
        wren_b                                  => '0',                   
        address_b                               => std_logic_vector(cos_addr),
        data_b                                  => (others =>'0'),
        q_b                                     => cos_data
        );
    
    
    main: process (clk)
    begin       
        if (rising_edge(clk)) then   
            
            if (Dien = '1') then   
                negs <= phi(14); 
                negc <= phi(14) xor phi(13);
                
                if (phi(14 downto 13) = "00" or phi(14 downto 13) = "10") then
                    sin_addr    <= phi(12 downto 0);
                else
                    if (phi(12 downto 0) = "0000000000000") then   
                        sin_addr  <= "1" & X"FFF";
                    else
                        sin_addr  <= std_logic_vector(resize((PI_POS - unsigned(phi(13 downto 0))),13));
                    end if; 
                end if;
                
                if (phi(14 downto 13) = "01" or phi(14 downto 13) = "11") then
                    cos_addr    <= phi(12 downto 0);
                else
                    if (phi(12 downto 0) = "0000000000000") then   
                        cos_addr  <= "1" & X"FFF";
                    else
                        cos_addr  <= std_logic_vector(resize((PI_POS - unsigned(phi(13 downto 0))),13));
                    end if;
                end if;   
            end if; --dien
            
                qqq_Dien <= qq_Dien; qq_Dien <= q_Dien; q_Dien <= Dien; 
                qqq_negs <= qq_negs; qq_negs <= q_negs; q_negs <= negs;
                qqq_negc <= qq_negc; qq_negc <= q_negc; q_negc <= negc;
                
                if qqq_Dien = '1' then      
                    if (qqq_negs = '0') then
                        sin <= sin_data;
                    else                  
                        sin <= std_logic_vector("0000000000000000" - unsigned(sin_data));
                    end if; 
                    
                    if (qqq_negc = '0') then
                        cos <= cos_data;
                    else                  
                        cos <= std_logic_vector("0000000000000000" - unsigned(cos_data));
                    end if;
                end if;
                Doen <= qqq_Dien;
            
        end if; --clk 
    end process;
end sin_cos_arch;