init_target.h

Bycore是一个嵌入式操作系统内核。Bycore包括内存管理、任务管理、中断管理、任务互斥、同步与通信管理等功能。Bycore全部由C语言完成

/**
 *  init_target.h - Some const value for initialization.
 *
 *  Copyright (C) 2008  ZhangHu
 *  All rights reserved.
 *  E-MAIL: [e-mail]
 *
 *  This program is free software: you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation, either version 3 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */


#ifndef __INIT_TARGET_H__
#define __INIT_TARGET_H__

/* BUSWIDTH; 16,32 */
#define BUSWIDTH	32

/* DRAM or SDRAM */
#ifdef  BDRAMTYPE_DRAM
#undef  BDRAMTYPE_DRAM
#endif

/* MEMORY CONTROL PARAMETERS */

/* Bank 0 parameter */
#define B0_Tacs		    0x0
#define B0_Tcos			0x0	/* 0clk */
#define B0_Tacc			0x6	/* 10clk */
#define B0_Tcoh			0x0	/* 0clk */
#define B0_Tah			0x0	/* 0clk */
#define B0_Tacp			0x0	/* 0clk */
#define B0_PMC			0x0	/* normal(1data) */

/* Bank 1 parameter */
#define B1_Tacs			0x3	/* 4clk */
#define B1_Tcos			0x3	/* 4clk */
#define B1_Tacc			0x7	/* 14clk */
#define B1_Tcoh			0x3	/* 4clk */
#define B1_Tah			0x3	/* 4clk */
#define B1_Tacp			0x3	/* 6clk */
#define B1_PMC			0x0	/* normal(1data) */

/* Bank 2 parameter */
#define B2_Tacs			0x3	/* 4clk */
#define B2_Tcos			0x3	/* 4clk */
#define B2_Tacc			0x7	/* 14clk */
#define B2_Tcoh			0x3	/* 4clk */
#define B2_Tah			0x3	/* 4clk */
#define B2_Tacp			0x3	/* 6clk */
#define B2_PMC			0x0	/* normal(1data) */

/* Bank 3 parameter */
#define B3_Tacs			0x3	/* 4clk */
#define B3_Tcos			0x3	/* 4clk */
#define B3_Tacc			0x7	/* 14clk */
#define B3_Tcoh			0x3	/* 4clk */
#define B3_Tah			0x3	/* 4clk */
#define B3_Tacp			0x3	/* 6clk */
#define B3_PMC			0x0	/* normal(1data) */

/* Bank 4 parameter */
#define B4_Tacs			0x3	/* 4clk */
#define B4_Tcos			0x3	/* 4clk */
#define B4_Tacc			0x7	/* 14clk */
#define B4_Tcoh			0x3	/* 4clk */
#define B4_Tah			0x3	/* 4clk */
#define B4_Tacp			0x3	/* 6clk */
#define B4_PMC			0x0	/* normal(1data) */

/* Bank 5 parameter */
#define B5_Tacs			0x3	/* 4clk */
#define B5_Tcos			0x3	/* 4clk */
#define B5_Tacc			0x7	/* 14clk */
#define B5_Tcoh			0x3	/* 4clk */
#define B5_Tah			0x3	/* 4clk */
#define B5_Tacp			0x3	/* 6clk */
#define B5_PMC			0x0	/* normal(1data) */

/* Bank 6(if SROM) parameter */
#define B6_Tacs			0x3	/* 4clk */
#define B6_Tcos			0x3	/* 4clk */
#define B6_Tacc			0x7	/* 14clk */
#define B6_Tcoh			0x3	/* 4clk */
#define B6_Tah			0x3	/* 4clk */
#define B6_Tacp			0x3	/* 6clk */
#define B6_PMC			0x0	/* normal(1data) */

/* Bank 7(if SROM) parameter */
#define B7_Tacs			0x3	/* 4clk */
#define B7_Tcos			0x3	/* 4clk */
#define B7_Tacc			0x7	/* 14clk */
#define B7_Tcoh			0x3	/* 4clk */
#define B7_Tah			0x3	/* 4clk */
#define B7_Tacp			0x3	/* 6clk */
#define B7_PMC			0x0	/* normal(1data) */

/* Bank 6 parameter */
#ifdef  BDRAMTYPE_DRAM  /* MT=01(FP DRAM) or 10(EDO DRAM)  */
#define B6_MT			  0x2	/* EDO DRAM */
#define B6_Trcd			0x0	/* 1clk */
#define B6_Tcas			0x0	/* 1clk */
#define B6_Tcp			0x0	/* 1clk */
#define B6_CAN			0x2	/* 10bit */
#else                   /* "SDRAM"		MT=11(SDRAM) */
#define B6_MT			  0x3	/* SDRAM */
#define B6_Trcd			0x0	/* 2clk */
#define B6_SCAN			0x0	/* 8bit */
#endif

/* Bank 7 parameter */
#ifdef  BDRAMTYPE_DRAM  /* MT=01(FP DRAM) or 10(EDO DRAM)  */
#define B7_MT			  0x2	/* EDO DRAM */
#define B7_Trcd			0x0	/* 2clk */
#define B7_Tcas			0x0	/* 2clk */
#define B7_Tcp			0x0	/* 2clk */
#define B7_CAN			0x2	/* 10bit */
#else                   /* "SDRAM"	MT=11(SDRAM) */
#define B7_MT			  0x3	/* SDRAM */
#define B7_Trcd			0x0	/* 2clk */
#define B7_SCAN			0x0	/* 8bit */
#endif

/* REFRESH parameter */
#define REFEN			  0x1	/* Refresh enable */
#define TREFMD			0x0	/* CBR(CAS before RAS)/Auto refresh */
#define Trp				  0x0	/* 2clk */
#define Trc				  0x0	/* 4clk */
#define Tchr			  0x2	/* 3clk */
#define REFCNT			1425/* period=15.6us, MCLK=40Mhz */

/**
 * PLL setup parameter
 */

#define PLLCLK	40000000  /* 66000000*/

#if	PLLCLK == 40000000	  /* Fin=10MHz Fout=40MHz */
#define M_DIV	0x48
#define P_DIV	0x3
#define S_DIV	0x2
#endif

#if	PLLCLK == 50000000	  /* Fin=10MHz Fout=50MHz */
#define M_DIV	0x2a
#define P_DIV	0x3
#define S_DIV	0x1
#endif

#if	PLLCLK == 60000000	  /* Fin=10MHz Fout=60MHz */
#define M_DIV	0x34
#define P_DIV	0x3
#define S_DIV	0x1
#endif

#if	PLLCLK == 66000000	  /* Fin=10MHz Fout=66MHz */
#define M_DIV	0x3a
#define P_DIV	0x3
#define S_DIV	0x1
#endif


#if PLLCLK == 75000000	  /* Fin=10MHz Fout=75MHz */
#define M_DIV	0x43
#define P_DIV	0x3
#define S_DIV	0x1
#endif
/* PLL setup parameter is end */

extern void init_target(void);

#endif