📄 usbbus.map.rpt
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Analysis & Synthesis report for usbbus
Wed Feb 15 15:38:57 2006
Version 4.0 Build 190 1/28/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Default Parameter Settings
5. Hierarchy
6. Analysis & Synthesis Resource Utilization by Entity
7. Analysis & Synthesis Equations
8. Analysis & Synthesis Files Read
9. Analysis & Synthesis Resource Usage Summary
10. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+---------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+---------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Feb 15 15:38:57 2006 ;
; Revision Name ; usbbus ;
; Top-level Entity Name ; usbbus ;
; Family ; MAX3000A ;
; Total macrocells ; 36 ;
; Total pins ; 59 ;
+-----------------------------+---------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+------------------------------------------------------------------------------------------------------
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------+--------------+---------------+
; Top-level entity name ; usbbus ; ;
; Family name ; MAX3000A ; Stratix ;
; Auto Resource Sharing ; Off ; Off ;
; Remove Duplicate Logic ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Auto Parallel Expanders ; On ; On ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4 ; 4 ;
; Auto Logic Cell Insertion ; On ; On ;
; Allow XOR Gate Usage ; On ; On ;
; Optimization Technique -- MAX 7000B/7000AE/3000A ; Speed ; Speed ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Off ; Off ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Auto ; Auto ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore CARRY Buffers ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Power-Up Don't Care ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; State Machine Processing ; Auto ; Auto ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; Preserve fewer node names ; On ; On ;
; Disk space/compilation speed tradeoff ; Normal ; Normal ;
; Create Debugging Nodes for IP Cores ; off ; off ;
+----------------------------------------------------------------------+--------------+---------------+
+-------------------------------------------------+
; Analysis & Synthesis Default Parameter Settings ;
+--------------------------------------------------
; Name ; Setting ;
+--------------------+----------------------------+
; CARRY_CHAIN ; MANUAL ;
; CASCADE_CHAIN ; MANUAL ;
; OPTIMIZE_FOR_SPEED ; 9 ;
; STYLE ; FAST ;
+--------------------+----------------------------+
+------------+
; Hierarchy ;
+------------+
usbbus
|-- 74244b:inst
|-- 74244b:inst4
+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-----------------------------------------------------------------------
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |usbbus ; 36 ; 59 ; |usbbus ;
+----------------------------+------------+------+---------------------+
+---------------------------------+
; Analysis & Synthesis Equations ;
+---------------------------------+
The equations can be found in F:/test/test/usbbus/usbbus.map.eqn.
+--------------------------------------------------------+
; Analysis & Synthesis Files Read ;
+---------------------------------------------------------
; File Name ; Read ;
+-------------------------------------------------+------+
; usbbus.bdf ; Read ;
; e:/quartus/libraries/others/maxplus2/74244b.bdf ; Read ;
+-------------------------------------------------+------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------------------------------
; Resource ; Usage ;
+----------------------+----------------------+
; Logic cells ; 36 ;
; I/O pins ; 59 ;
; Maximum fan-out node ; WR ;
; Maximum fan-out ; 9 ;
; Total fan-out ; 88 ;
; Average fan-out ; 0.93 ;
+----------------------+----------------------+
+--------------------------------+
; Analysis & Synthesis Messages ;
+--------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
Info: Processing started: Wed Feb 15 15:38:56 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off usbbus -c usbbus
Info: Found 1 design units and 1 entities in source file usbbus.bdf
Info: Found entity 1: usbbus
Warning: Pin EA not connected
Warning: Pin ALE not connected
Warning: Pin PSEN not connected
Warning: Primitive VCC of instance inst2 not used
Info: Found 1 design units and 1 entities in source file e:/quartus/libraries/others/maxplus2/74244b.bdf
Info: Found entity 1: 74244b
Warning: Design contains 3 input pin(s) that do not drive logic
Warning: No output dependent on input pin EA
Warning: No output dependent on input pin ALE
Warning: No output dependent on input pin PSEN
Info: Implemented 95 device resources after synthesis - the final resource count might be different
Info: Implemented 23 input pins
Info: Implemented 20 output pins
Info: Implemented 16 bidirectional pins
Info: Implemented 36 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings
Info: Processing ended: Wed Feb 15 15:38:57 2006
Info: Elapsed time: 00:00:00
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