test.map.rpt

实现了对SD卡的SPI方式下读写操作

; Auto Open-Drain Pins                                           ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                          ; Off                ; Off                ;
; Perform gate-level register retiming                           ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax         ; On                 ; On                 ;
; Auto ROM Replacement                                           ; On                 ; On                 ;
; Auto RAM Replacement                                           ; On                 ; On                 ;
; Auto Shift Register Replacement                                ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                  ; On                 ; On                 ;
; Strict RAM Replacement                                         ; Off                ; Off                ;
; Allow Synchronous Control Signals                              ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                         ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                              ; Off                ; Off                ;
; Auto Resource Sharing                                          ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                             ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                             ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                  ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing            ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives              ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                             ; Off                ; Off                ;
; Synchronization Register Chain Length                          ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report       ; 100                ; 100                ;
; Number of Inverted Registers Reported in Synthesis Report      ; 100                ; 100                ;
; Clock MUX Protection                                           ; On                 ; On                 ;
; Auto Gated Clock Conversion                                    ; Off                ; Off                ;
; Block Design Naming                                            ; Auto               ; Auto               ;
; SDC constraint protection                                      ; Off                ; Off                ;
; Synthesis Effort                                               ; Auto               ; Auto               ;
; Allows Asynchronous Clear Usage For Shift Register Replacement ; On                 ; On                 ;
; Analysis & Synthesis Message Level                             ; Medium             ; Medium             ;
+----------------------------------------------------------------+--------------------+--------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                   ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                   ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+
; counter.vhd                      ; yes             ; User VHDL File                     ; E:/spi_Master/counter.vhd                                      ;
; datasource.vhd                   ; yes             ; User VHDL File                     ; E:/spi_Master/datasource.vhd                                   ;
; pll48m.vhd                       ; yes             ; User Wizard-Generated File         ; E:/spi_Master/pll48m.vhd                                       ;
; test.bdf                         ; yes             ; User Block Diagram/Schematic File  ; E:/spi_Master/test.bdf                                         ;
; RTL/ctrlStsRegBI.v               ; yes             ; User Verilog HDL File              ; E:/spi_Master/RTL/ctrlStsRegBI.v                               ;
; RTL/initSD.v                     ; yes             ; User Verilog HDL File              ; E:/spi_Master/RTL/initSD.v                                     ;
; RTL/readWriteSDBlock.v           ; yes             ; User Verilog HDL File              ; E:/spi_Master/RTL/readWriteSDBlock.v                           ;
; RTL/readWriteSPIWireData.v       ; yes             ; User Verilog HDL File              ; E:/spi_Master/RTL/readWriteSPIWireData.v                       ;
; RTL/sendCmd.v                    ; yes             ; User Verilog HDL File              ; E:/spi_Master/RTL/sendCmd.v                                    ;
; RTL/sm_dpMem_dc.v                ; yes             ; User Verilog HDL File              ; E:/spi_Master/RTL/sm_dpMem_dc.v                                ;
; RTL/sm_fifoRTL.v                 ; yes             ; User Verilog HDL File              ; E:/spi_Master/RTL/sm_fifoRTL.v                                 ;
; RTL/sm_RxFifo.v                  ; yes             ; User Verilog HDL File              ; E:/spi_Master/RTL/sm_RxFifo.v                                  ;
; RTL/sm_RxFifoBI.v                ; yes             ; User Verilog HDL File              ; E:/spi_Master/RTL/sm_RxFifoBI.v                                ;
; RTL/sm_TxFifo.v                  ; yes             ; User Verilog HDL File              ; E:/spi_Master/RTL/sm_TxFifo.v                                  ;
; RTL/sm_TxFifoBI.v                ; yes             ; User Verilog HDL File              ; E:/spi_Master/RTL/sm_TxFifoBI.v                                ;
; RTL/spiCtrl.v                    ; yes             ; User Verilog HDL File              ; E:/spi_Master/RTL/spiCtrl.v                                    ;
; RTL/spiMaster.v                  ; yes             ; User Verilog HDL File              ; E:/spi_Master/RTL/spiMaster.v                                  ;
; RTL/spiMaster_defines.v          ; yes             ; User Verilog HDL File              ; E:/spi_Master/RTL/spiMaster_defines.v                          ;
; RTL/spiMasterWishBoneBI.v        ; yes             ; User Verilog HDL File              ; E:/spi_Master/RTL/spiMasterWishBoneBI.v                        ;