prev_cmp_test.qmsg

实现了对SD卡的SPI方式下读写操作

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RTL/spiMaster_defines.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file RTL/spiMaster_defines.v" {  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RTL/spiMasterWishBoneBI.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file RTL/spiMasterWishBoneBI.v" { { "Info" "ISGN_ENTITY_NAME" "1 spiMasterWishBoneBI " "Info: Found entity 1: spiMasterWishBoneBI" {  } { { "RTL/spiMasterWishBoneBI.v" "" { Text "E:/spi_Master/RTL/spiMasterWishBoneBI.v" 48 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RTL/spiTxRxData.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file RTL/spiTxRxData.v" { { "Info" "ISGN_ENTITY_NAME" "1 spiTxRxData " "Info: Found entity 1: spiTxRxData" {  } { { "RTL/spiTxRxData.v" "" { Text "E:/spi_Master/RTL/spiTxRxData.v" 48 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RTL/timescale.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file RTL/timescale.v" {  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "ctrlStsRegSel spiMaster.v(148) " "Warning (10236): Verilog HDL Implicit Net warning at spiMaster.v(148): created implicit net for \"ctrlStsRegSel\"" {  } { { "RTL/spiMaster.v" "" { Text "E:/spi_Master/RTL/spiMaster.v" 148 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "rxFifoSel spiMaster.v(155) " "Warning (10236): Verilog HDL Implicit Net warning at spiMaster.v(155): created implicit net for \"rxFifoSel\"" {  } { { "RTL/spiMaster.v" "" { Text "E:/spi_Master/RTL/spiMaster.v" 155 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "txFifoSel spiMaster.v(157) " "Warning (10236): Verilog HDL Implicit Net warning at spiMaster.v(157): created implicit net for \"txFifoSel\"" {  } { { "RTL/spiMaster.v" "" { Text "E:/spi_Master/RTL/spiMaster.v" 157 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "rstSyncToBusClk spiMaster.v(167) " "Warning (10236): Verilog HDL Implicit Net warning at spiMaster.v(167): created implicit net for \"rstSyncToBusClk\"" {  } { { "RTL/spiMaster.v" "" { Text "E:/spi_Master/RTL/spiMaster.v" 167 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "spiTransCtrl spiMaster.v(176) " "Warning (10236): Verilog HDL Implicit Net warning at spiMaster.v(176): created implicit net for \"spiTransCtrl\"" {  } { { "RTL/spiMaster.v" "" { Text "E:/spi_Master/RTL/spiMaster.v" 176 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "spiTransSts spiMaster.v(177) " "Warning (10236): Verilog HDL Implicit Net warning at spiMaster.v(177): created implicit net for \"spiTransSts\"" {  } { { "RTL/spiMaster.v" "" { Text "E:/spi_Master/RTL/spiMaster.v" 177 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "SDInitReq spiMaster.v(194) " "Warning (10236): Verilog HDL Implicit Net warning at spiMaster.v(194): created implicit net for \"SDInitReq\"" {  } { { "RTL/spiMaster.v" "" { Text "E:/spi_Master/RTL/spiMaster.v" 194 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "SDInitRdy spiMaster.v(195) " "Warning (10236): Verilog HDL Implicit Net warning at spiMaster.v(195): created implicit net for \"SDInitRdy\"" {  } { { "RTL/spiMaster.v" "" { Text "E:/spi_Master/RTL/spiMaster.v" 195 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "readWriteSDBlockRdy spiMaster.v(197) " "Warning (10236): Verilog HDL Implicit Net warning at spiMaster.v(197): created implicit net for \"readWriteSDBlockRdy\"" {  } { { "RTL/spiMaster.v" "" { Text "E:/spi_Master/RTL/spiMaster.v" 197 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "rxDataRdyFromSpiTxRxData spiMaster.v(198) " "Warning (10236): Verilog HDL Implicit Net warning at spiMaster.v(198): created implicit net for \"rxDataRdyFromSpiTxRxData\"" {  } { { "RTL/spiMaster.v" "" { Text "E:/spi_Master/RTL/spiMaster.v" 198 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "rxDataRdyClrFromSpiCtrl spiMaster.v(199) " "Warning (10236): Verilog HDL Implicit Net warning at spiMaster.v(199): created implicit net for \"rxDataRdyClrFromSpiCtrl\"" {  } { { "RTL/spiMaster.v" "" { Text "E:/spi_Master/RTL/spiMaster.v" 199 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "txDataWenFromSpiCtrl spiMaster.v(203) " "Warning (10236): Verilog HDL Implicit Net warning at spiMaster.v(203): created implicit net for \"txDataWenFromSpiCtrl\"" {  } { { "RTL/spiMaster.v" "" { Text "E:/spi_Master/RTL/spiMaster.v" 203 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "sendCmdReqFromInitSD spiMaster.v(217) " "Warning (10236): Verilog HDL Implicit Net warning at spiMaster.v(217): created implicit net for \"sendCmdReqFromInitSD\"" {  } { { "RTL/spiMaster.v" "" { Text "E:/spi_Master/RTL/spiMaster.v" 217 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "sendCmdRdy spiMaster.v(218) " "Warning (10236): Verilog HDL Implicit Net warning at spiMaster.v(218): created implicit net for \"sendCmdRdy\"" {  } { { "RTL/spiMaster.v" "" { Text "E:/spi_Master/RTL/spiMaster.v" 218 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "sendCmdRespTout spiMaster.v(226) " "Warning (10236): Verilog HDL Implicit Net warning at spiMaster.v(226): created implicit net for \"sendCmdRespTout\"" {  } { { "RTL/spiMaster.v" "" { Text "E:/spi_Master/RTL/spiMaster.v" 226 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "txDataEmptyFromRWSPIWireData spiMaster.v(231) " "Warning (10236): Verilog HDL Implicit Net warning at spiMaster.v(231): created implicit net for \"txDataEmptyFromRWSPIWireData\"" {  } { { "RTL/spiMaster.v" "" { Text "E:/spi_Master/RTL/spiMaster.v" 231 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}