test.map.qmsg

实现了对SD卡的SPI方式下读写操作

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sm_RxFifo spiMaster:inst\|sm_RxFifo:u_sm_rxFifo " "Info: Elaborating entity \"sm_RxFifo\" for hierarchy \"spiMaster:inst\|sm_RxFifo:u_sm_rxFifo\"" {  } { { "RTL/spiMaster.v" "u_sm_rxFifo" { Text "E:/spi_Master/RTL/spiMaster.v" 380 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sm_RxfifoBI spiMaster:inst\|sm_RxFifo:u_sm_rxFifo\|sm_RxfifoBI:u_sm_RxfifoBI " "Info: Elaborating entity \"sm_RxfifoBI\" for hierarchy \"spiMaster:inst\|sm_RxFifo:u_sm_rxFifo\|sm_RxfifoBI:u_sm_RxfifoBI\"" {  } { { "RTL/sm_RxFifo.v" "u_sm_RxfifoBI" { Text "E:/spi_Master/RTL/sm_RxFifo.v" 132 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "datasource datasource:inst1 " "Info: Elaborating entity \"datasource\" for hierarchy \"datasource:inst1\"" {  } { { "test.bdf" "inst1" { Schematic "E:/spi_Master/test.bdf" { { 168 64 296 360 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "rstout datasource.vhd(11) " "Warning (10541): VHDL Signal Declaration warning at datasource.vhd(11): used implicit default value for signal \"rstout\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "datasource.vhd" "" { Text "E:/spi_Master/datasource.vhd" 11 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "counterout datasource.vhd(29) " "Warning (10036): Verilog HDL or VHDL warning at datasource.vhd(29): object \"counterout\" assigned a value but never read" {  } { { "datasource.vhd" "" { Text "E:/spi_Master/datasource.vhd" 29 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "tmp1 datasource.vhd(185) " "Warning (10492): VHDL Process Statement warning at datasource.vhd(185): signal \"tmp1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "datasource.vhd" "" { Text "E:/spi_Master/datasource.vhd" 185 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "addressout datasource.vhd(182) " "Warning (10631): VHDL Process Statement warning at datasource.vhd(182): inferring latch(es) for signal or variable \"addressout\", which holds its previous value in one or more paths through the process" {  } { { "datasource.vhd" "" { Text "E:/spi_Master/datasource.vhd" 182 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "datainout datasource.vhd(182) " "Warning (10631): VHDL Process Statement warning at datasource.vhd(182): inferring latch(es) for signal or variable \"datainout\", which holds its previous value in one or more paths through the process" {  } { { "datasource.vhd" "" { Text "E:/spi_Master/datasource.vhd" 182 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "strobeout datasource.vhd(182) " "Warning (10631): VHDL Process Statement warning at datasource.vhd(182): inferring latch(es) for signal or variable \"strobeout\", which holds its previous value in one or more paths through the process" {  } { { "datasource.vhd" "" { Text "E:/spi_Master/datasource.vhd" 182 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "writenout datasource.vhd(182) " "Warning (10631): VHDL Process Statement warning at datasource.vhd(182): inferring latch(es) for signal or variable \"writenout\", which holds its previous value in one or more paths through the process" {  } { { "datasource.vhd" "" { Text "E:/spi_Master/datasource.vhd" 182 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "writenout datasource.vhd(182) " "Info (10041): Inferred latch for \"writenout\" at datasource.vhd(182)" {  } { { "datasource.vhd" "" { Text "E:/spi_Master/datasource.vhd" 182 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "strobeout datasource.vhd(182) " "Info (10041): Inferred latch for \"strobeout\" at datasource.vhd(182)" {  } { { "datasource.vhd" "" { Text "E:/spi_Master/datasource.vhd" 182 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "datainout\[0\] datasource.vhd(182) " "Info (10041): Inferred latch for \"datainout\[0\]\" at datasource.vhd(182)" {  } { { "datasource.vhd" "" { Text "E:/spi_Master/datasource.vhd" 182 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "datainout\[1\] datasource.vhd(182) " "Info (10041): Inferred latch for \"datainout\[1\]\" at datasource.vhd(182)" {  } { { "datasource.vhd" "" { Text "E:/spi_Master/datasource.vhd" 182 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "datainout\[2\] datasource.vhd(182) " "Info (10041): Inferred latch for \"datainout\[2\]\" at datasource.vhd(182)" {  } { { "datasource.vhd" "" { Text "E:/spi_Master/datasource.vhd" 182 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "datainout\[3\] datasource.vhd(182) " "Info (10041): Inferred latch for \"datainout\[3\]\" at datasource.vhd(182)" {  } { { "datasource.vhd" "" { Text "E:/spi_Master/datasource.vhd" 182 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "datainout\[4\] datasource.vhd(182) " "Info (10041): Inferred latch for \"datainout\[4\]\" at datasource.vhd(182)" {  } { { "datasource.vhd" "" { Text "E:/spi_Master/datasource.vhd" 182 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "datainout\[5\] datasource.vhd(182) " "Info (10041): Inferred latch for \"datainout\[5\]\" at datasource.vhd(182)" {  } { { "datasource.vhd" "" { Text "E:/spi_Master/datasource.vhd" 182 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "datainout\[6\] datasource.vhd(182) " "Info (10041): Inferred latch for \"datainout\[6\]\" at datasource.vhd(182)" {  } { { "datasource.vhd" "" { Text "E:/spi_Master/datasource.vhd" 182 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "datainout\[7\] datasource.vhd(182) " "Info (10041): Inferred latch for \"datainout\[7\]\" at datasource.vhd(182)" {  } { { "datasource.vhd" "" { Text "E:/spi_Master/datasource.vhd" 182 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}