test.map.qmsg

实现了对SD卡的SPI方式下读写操作

{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "rxDataRdyClrFromInitSD spiMaster.v(235) " "Warning (10236): Verilog HDL Implicit Net warning at spiMaster.v(235): created implicit net for \"rxDataRdyClrFromInitSD\"" {  } { { "RTL/spiMaster.v" "" { Text "E:/spi_Master/RTL/spiMaster.v" 235 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "sendCmdReqFromRWSDBlock spiMaster.v(259) " "Warning (10236): Verilog HDL Implicit Net warning at spiMaster.v(259): created implicit net for \"sendCmdReqFromRWSDBlock\"" {  } { { "RTL/spiMaster.v" "" { Text "E:/spi_Master/RTL/spiMaster.v" 259 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "txFifoRE spiMaster.v(266) " "Warning (10236): Verilog HDL Implicit Net warning at spiMaster.v(266): created implicit net for \"txFifoRE\"" {  } { { "RTL/spiMaster.v" "" { Text "E:/spi_Master/RTL/spiMaster.v" 266 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "rRxFifoWE spiMaster.v(268) " "Warning (10236): Verilog HDL Implicit Net warning at spiMaster.v(268): created implicit net for \"rRxFifoWE\"" {  } { { "RTL/spiMaster.v" "" { Text "E:/spi_Master/RTL/spiMaster.v" 268 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "hostTxFifoEmpty spiMaster.v(357) " "Warning (10236): Verilog HDL Implicit Net warning at spiMaster.v(357): created implicit net for \"hostTxFifoEmpty\"" {  } { { "RTL/spiMaster.v" "" { Text "E:/spi_Master/RTL/spiMaster.v" 357 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "hostRxFifoFull spiMaster.v(373) " "Warning (10236): Verilog HDL Implicit Net warning at spiMaster.v(373): created implicit net for \"hostRxFifoFull\"" {  } { { "RTL/spiMaster.v" "" { Text "E:/spi_Master/RTL/spiMaster.v" 373 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "test " "Info: Elaborating entity \"test\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spiMaster spiMaster:inst " "Info: Elaborating entity \"spiMaster\" for hierarchy \"spiMaster:inst\"" {  } { { "test.bdf" "inst" { Schematic "E:/spi_Master/test.bdf" { { 144 456 640 336 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spiMasterWishBoneBI spiMaster:inst\|spiMasterWishBoneBI:u_spiMasterWishBoneBI " "Info: Elaborating entity \"spiMasterWishBoneBI\" for hierarchy \"spiMaster:inst\|spiMasterWishBoneBI:u_spiMasterWishBoneBI\"" {  } { { "RTL/spiMaster.v" "u_spiMasterWishBoneBI" { Text "E:/spi_Master/RTL/spiMaster.v" 159 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ctrlStsRegBI spiMaster:inst\|ctrlStsRegBI:u_ctrlStsRegBI " "Info: Elaborating entity \"ctrlStsRegBI\" for hierarchy \"spiMaster:inst\|ctrlStsRegBI:u_ctrlStsRegBI\"" {  } { { "RTL/spiMaster.v" "u_ctrlStsRegBI" { Text "E:/spi_Master/RTL/spiMaster.v" 186 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spiCtrl spiMaster:inst\|spiCtrl:u_spiCtrl " "Info: Elaborating entity \"spiCtrl\" for hierarchy \"spiMaster:inst\|spiCtrl:u_spiCtrl\"" {  } { { "RTL/spiMaster.v" "u_spiCtrl" { Text "E:/spi_Master/RTL/spiMaster.v" 205 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "initSD spiMaster:inst\|initSD:u_initSD " "Info: Elaborating entity \"initSD\" for hierarchy \"spiMaster:inst\|initSD:u_initSD\"" {  } { { "RTL/spiMaster.v" "u_initSD" { Text "E:/spi_Master/RTL/spiMaster.v" 236 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "readWriteSDBlock spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock " "Info: Elaborating entity \"readWriteSDBlock\" for hierarchy \"spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\"" {  } { { "RTL/spiMaster.v" "u_readWriteSDBlock" { Text "E:/spi_Master/RTL/spiMaster.v" 272 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sendCmd spiMaster:inst\|sendCmd:u_sendCmd " "Info: Elaborating entity \"sendCmd\" for hierarchy \"spiMaster:inst\|sendCmd:u_sendCmd\"" {  } { { "RTL/spiMaster.v" "u_sendCmd" { Text "E:/spi_Master/RTL/spiMaster.v" 304 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spiTxRxData spiMaster:inst\|spiTxRxData:u_spiTxRxData " "Info: Elaborating entity \"spiTxRxData\" for hierarchy \"spiMaster:inst\|spiTxRxData:u_spiTxRxData\"" {  } { { "RTL/spiMaster.v" "u_spiTxRxData" { Text "E:/spi_Master/RTL/spiMaster.v" 331 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "readWriteSPIWireData spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData " "Info: Elaborating entity \"readWriteSPIWireData\" for hierarchy \"spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\"" {  } { { "RTL/spiMaster.v" "u_readWriteSPIWireData" { Text "E:/spi_Master/RTL/spiMaster.v" 349 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sm_TxFifo spiMaster:inst\|sm_TxFifo:u_sm_txFifo " "Info: Elaborating entity \"sm_TxFifo\" for hierarchy \"spiMaster:inst\|sm_TxFifo:u_sm_txFifo\"" {  } { { "RTL/spiMaster.v" "u_sm_txFifo" { Text "E:/spi_Master/RTL/spiMaster.v" 364 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sm_fifoRTL spiMaster:inst\|sm_TxFifo:u_sm_txFifo\|sm_fifoRTL:u_sm_fifo " "Info: Elaborating entity \"sm_fifoRTL\" for hierarchy \"spiMaster:inst\|sm_TxFifo:u_sm_txFifo\|sm_fifoRTL:u_sm_fifo\"" {  } { { "RTL/sm_TxFifo.v" "u_sm_fifo" { Text "E:/spi_Master/RTL/sm_TxFifo.v" 114 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sm_dpMem_dc spiMaster:inst\|sm_TxFifo:u_sm_txFifo\|sm_fifoRTL:u_sm_fifo\|sm_dpMem_dc:u_sm_dpMem_dc " "Info: Elaborating entity \"sm_dpMem_dc\" for hierarchy \"spiMaster:inst\|sm_TxFifo:u_sm_txFifo\|sm_fifoRTL:u_sm_fifo\|sm_dpMem_dc:u_sm_dpMem_dc\"" {  } { { "RTL/sm_fifoRTL.v" "u_sm_dpMem_dc" { Text "E:/spi_Master/RTL/sm_fifoRTL.v" 162 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sm_TxfifoBI spiMaster:inst\|sm_TxFifo:u_sm_txFifo\|sm_TxfifoBI:u_sm_TxfifoBI " "Info: Elaborating entity \"sm_TxfifoBI\" for hierarchy \"spiMaster:inst\|sm_TxFifo:u_sm_txFifo\|sm_TxfifoBI:u_sm_TxfifoBI\"" {  } { { "RTL/sm_TxFifo.v" "u_sm_TxfifoBI" { Text "E:/spi_Master/RTL/sm_TxFifo.v" 130 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}