📄 test.hif

📁 实现了对SD卡的SPI方式下读写操作
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Version 8.1 Build 163 10/28/2008 SJ Full Version
11
919
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
test
# storage
db|test.(0).cnf
db|test.(0).cnf
# case_insensitive
# source_file
test.bdf
b7f3d79c2491e76a9d474489c14cb1
26
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
|
}
# macro_sequence

# end
# entity
spiMaster
# storage
db|test.(1).cnf
db|test.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RTL|spiMaster.v
f334af788828ed1bde9e9fb7ad4e768
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# include_file {
RTL|timescale.v
90acbbce5b36e269c098dfecb82797
RTL|spiMaster_defines.v
f1748e4cb2521cee5037f75263ccf249
}
# hierarchies {
spiMaster:inst
}
# macro_sequence
TX_FIFO_DEPTH512TX_FIFO_ADDR_WIDTH9RX_FIFO_DEPTH512RX_FIFO_ADDR_WIDTH9SPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZ
# end
# entity
spiMasterWishBoneBI
# storage
db|test.(2).cnf
db|test.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RTL|spiMasterWishBoneBI.v
d0eaa839d5f960a159cf9c7847b67d8e
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# include_file {
RTL|timescale.v
90acbbce5b36e269c098dfecb82797
RTL|spiMaster_defines.v
f1748e4cb2521cee5037f75263ccf249
}
# hierarchies {
spiMaster:inst|spiMasterWishBoneBI:u_spiMasterWishBoneBI
}
# macro_sequence
ADDRESS_DECODE_MASK8'hf0CTRL_STS_REG_BASE8'h00RX_FIFO_BASE8'h10TX_FIFO_BASE8'h20RX_FIFO_BASE8'h10FIFO_DATA_REG3'b000TX_FIFO_BASE8'h20FIFO_DATA_REG3'b000SPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZ
# end
# entity
ctrlStsRegBI
# storage
db|test.(3).cnf
db|test.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RTL|ctrlStsRegBI.v
7b649c546266f963cb3ebbfdd16724c
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# include_file {
RTL|timescale.v
90acbbce5b36e269c098dfecb82797
RTL|spiMaster_defines.v
f1748e4cb2521cee5037f75263ccf249
}
# hierarchies {
spiMaster:inst|ctrlStsRegBI:u_ctrlStsRegBI
}
# macro_sequence
DIRECT_ACCESS2'b00TRANS_STOP1'b0FAST_SPI_CLK8'h00SPI_MASTER_CONTROL_REG8'h01TRANS_CTRL_REG8'h03TRANS_TYPE_REG8'h02SD_ADDR_7_0_REG8'h07SD_ADDR_15_8_REG8'h08SD_ADDR_23_16_REG8'h09SD_ADDR_31_24_REG8'h0aSPI_CLK_DEL_REG8'h0bDIRECT_ACCESS_DATA_REG8'h06SPI_MASTER_VERSION_REG8'h00SPI_MASTER_VERSION_NUM8'h12TRANS_TYPE_REG8'h02TRANS_CTRL_REG8'h03TRANS_STS_REG8'h04TRANS_ERROR_REG8'h05SD_ADDR_7_0_REG8'h07SD_ADDR_15_8_REG8'h08SD_ADDR_23_16_REG8'h09SD_ADDR_31_24_REG8'h0aSPI_CLK_DEL_REG8'h0bDIRECT_ACCESS_DATA_REG8'h06TRANS_START1'b1TRANS_STOP1'b0DIRECT_ACCESS2'b00TRANS_NOT_BUSY1'b0TRANS_NOT_BUSY1'b0TRANS_NOT_BUSY1'b0TRANS_NOT_BUSY1'b0TRANS_START1'b1TRANS_BUSY1'b1TRANS_BUSY1'b1TRANS_NOT_BUSY1'b0TRANS_NOT_BUSY1'b0SPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZ
# end
# entity
spiCtrl
# storage
db|test.(4).cnf
db|test.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RTL|spiCtrl.v
2fdcacaff44c7ac4eeae49be92aa357
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# include_file {
RTL|timescale.v
90acbbce5b36e269c098dfecb82797
RTL|spiMaster_defines.v
f1748e4cb2521cee5037f75263ccf249
}
# hierarchies {
spiMaster:inst|spiCtrl:u_spiCtrl
}
# macro_sequence
ST_S_CTRL3'b000NO_BLOCK_REQ2'b00TRANS_NOT_BUSY1'b0WT_S_CTRL_REQ3'b001WT_S_CTRL_REQ3'b001TRANS_NOT_BUSY1'b0TRANS_START1'b1INIT_SD2'b01INIT3'b100TRANS_BUSY1'b1TRANS_START1'b1RW_WRITE_SD_BLOCK2'b11RW3'b110TRANS_BUSY1'b1WRITE_SD_BLOCK2'b01TRANS_START1'b1RW_READ_SD_BLOCK2'b10RW3'b110TRANS_BUSY1'b1READ_SD_BLOCK2'b10TRANS_START1'b1DIRECT_ACCESS2'b00DIR_ACC3'b011TRANS_BUSY1'b1WT_FIN13'b010WT_S_CTRL_REQ3'b001DIR_ACC3'b011WT_FIN13'b010INIT3'b100WT_FIN23'b101WT_FIN23'b101WT_S_CTRL_REQ3'b001RW3'b110NO_BLOCK_REQ2'b00WT_FIN33'b111WT_FIN33'b111WT_S_CTRL_REQ3'b001ST_S_CTRL3'b000NO_BLOCK_REQ2'b00TRANS_NOT_BUSY1'b0SPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZ
# end
# entity
initSD
# storage
db|test.(5).cnf
db|test.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RTL|initSD.v
c9f1296c3d7e7a4e032b175723b390
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# include_file {
RTL|timescale.v
90acbbce5b36e269c098dfecb82797
RTL|spiMaster_defines.v
f1748e4cb2521cee5037f75263ccf249
}
# hierarchies {
spiMaster:inst|initSD:u_initSD
}
# macro_sequence
START4'b0000INIT_NO_ERROR2'b00WT_INIT_REQ4'b0001WT_INIT_REQ4'b0001CLK_SEQ_SEND_FF4'b0010SLOW_SPI_CLK8'h3bINIT_NO_ERROR2'b00CLK_SEQ_SEND_FF4'b0010CLK_SEQ_CHK_FIN4'b0011CLK_SEQ_CHK_FIN4'b0011SD_INIT_START_SEQ_LEN8'ha0CLK_SEQ_WT_DATA_EMPTY4'b1101CLK_SEQ_SEND_FF4'b0010CLK_SEQ_WT_DATA_EMPTY4'b1101RESET_SEND_CMD4'b0100RESET_SEND_CMD4'b0100RESET_DEL4'b0101RESET_DEL4'b0101RESET_WT_FIN4'b0110RESET_WT_FIN4'b0110RESET_CHK_FIN4'b0111RESET_CHK_FIN4'b0111RESET_SEND_CMD4'b0100WT_INIT_REQ4'b0001INIT_CMD0_ERROR2'b01INIT_SEND_CMD4'b1010INIT_WT_FIN4'b1000INIT_CHK_FIN4'b1001INIT_CHK_FIN4'b1001INIT_SEND_CMD4'b1010WT_INIT_REQ4'b0001INIT_CMD1_ERROR2'b10WT_INIT_REQ4'b0001INIT_SEND_CMD4'b1010INIT_DEL14'b1011INIT_DEL14'b1011TWO_MS10'h177INIT_WT_FIN4'b1000INIT_DEL24'b1100INIT_DEL24'b1100INIT_DEL14'b1011START4'b0000INIT_NO_ERROR2'b00SPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZ
# end
# entity
readWriteSDBlock
# storage
db|test.(6).cnf
db|test.(6).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RTL|readWriteSDBlock.v
d012cf7b75398ed2fe78576099e95996
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# include_file {
RTL|timescale.v
90acbbce5b36e269c098dfecb82797
RTL|spiMaster_defines.v
f1748e4cb2521cee5037f75263ccf249
}
# hierarchies {
spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock
}
# macro_sequence
ST_RW_SD6'b000000READ_NO_ERROR2'b00WRITE_NO_ERROR2'b00WT_REQ6'b000100WT_REQ6'b000100READ_SD_BLOCK2'b10RD_CMD_SEND_CMD6'b010111READ_NO_ERROR2'b00WRITE_SD_BLOCK2'b01WR_CMD_SEND_CMD6'b000001WRITE_NO_ERROR2'b00WR_CMD_SEND_CMD6'b000001WR_CMD_DEL6'b000011WR_CMD_WT_FIN6'b000010WT_REQ6'b000100WRITE_CMD_ERROR2'b01WR_TOKEN_FF1_ST6'b000110WR_CMD_DEL6'b000011WR_CMD_WT_FIN6'b000010WR_TOKEN_FF1_FIN6'b000101WR_TOKEN_FF2_ST6'b001000WR_TOKEN_FF1_ST6'b000110WR_TOKEN_FF1_FIN6'b000101WR_TOKEN_FF2_FIN6'b000111WR_TOKEN_FE_ST6'b001010WR_TOKEN_FF2_ST6'b001000WR_TOKEN_FF2_FIN6'b000111WR_TOKEN_FE_FIN6'b001001WR_DATA_LOOP_INIT6'b001111WR_TOKEN_FE_ST6'b001010WR_TOKEN_FE_FIN6'b001001WR_BUSY_CHK_FIN6'b101000TWO_FIFTY_MS12'h0b6WR_BUSY_SEND_CMD16'b101011TWO_FIFTY_MS12'h0b6WT_REQ6'b000100WRITE_BUSY_ERROR2'b11WT_REQ6'b000100WR_BUSY_WT_FIN16'b101001WR_BUSY_CHK_FIN6'b101000WR_BUSY_DEL16'b101010MAX_8_BIT8'hffWR_BUSY_WT_FIN16'b101001WR_BUSY_DEL26'b101100WR_BUSY_SEND_CMD16'b101011WR_BUSY_DEL16'b101010WR_BUSY_DEL26'b101100WR_BUSY_DEL16'b101010WR_BUSY_INIT_LOOP6'b101101WR_BUSY_SEND_CMD16'b101011RD_CMD_SEND_CMD6'b010111RD_CMD_DEL6'b011001RD_CMD_WT_FIN6'b011000WT_REQ6'b000100READ_CMD_ERROR2'b01RD_TOKEN_INIT_LOOP6'b011110RD_CMD_DEL6'b011001RD_CMD_WT_FIN6'b011000RD_TOKEN_CHK_LOOP6'b011010ONE_HUNDRED_MS12'h048RD_TOKEN_DEL26'b011101ONE_HUNDRED_MS12'h048WT_REQ6'b000100READ_TOKEN_ERROR2'b10RD_DATA_CLR_RX6'b100011RD_TOKEN_WT_FIN6'b011011RD_TOKEN_CHK_LOOP6'b011010RD_TOKEN_SEND_CMD6'b011100RD_TOKEN_DEL16'b011111RD_TOKEN_DEL26'b011101MAX_8_BIT8'hffRD_TOKEN_SEND_CMD6'b011100RD_TOKEN_DEL36'b101110RD_TOKEN_INIT_LOOP6'b011110RD_TOKEN_SEND_CMD6'b011100RD_TOKEN_DEL16'b011111RD_TOKEN_WT_FIN6'b011011RD_TOKEN_DEL36'b101110RD_TOKEN_DEL26'b011101RD_DATA_ST_LOOP6'b100000RD_DATA_WT_DATA6'b100001RD_DATA_WT_DATA6'b100001RD_DATA_CHK_LOOP6'b100010RD_DATA_CHK_LOOP6'b100010RD_DATA_CS_ST16'b100110RD_DATA_ST_LOOP6'b100000RD_DATA_CLR_RX6'b100011RD_DATA_ST_LOOP6'b100000RD_DATA_CS_FIN26'b100100WT_REQ6'b000100RD_DATA_CS_FIN16'b100101RD_DATA_CS_ST26'b100111RD_DATA_CS_ST16'b100110RD_DATA_CS_FIN16'b100101RD_DATA_CS_ST26'b100111RD_DATA_CS_FIN26'b100100WR_DATA_D_FIN6'b001011WR_DATA_CS_ST16'b010000WR_DATA_RD_FIFO16'b001101WR_DATA_D_ST6'b001100WR_DATA_D_FIN6'b001011WR_DATA_RD_FIFO16'b001101WR_DATA_RD_FIFO26'b001110WR_DATA_RD_FIFO26'b001110WR_DATA_D_ST6'b001100WR_DATA_LOOP_INIT6'b001111WR_DATA_RD_FIFO16'b001101WR_DATA_CS_ST16'b010000WR_DATA_CS_FIN16'b010001WR_DATA_CS_FIN16'b010001WR_DATA_CS_ST26'b010011WR_DATA_CS_FIN26'b010010WR_DATA_REQ_RESP_ST6'b010101WR_DATA_CS_ST26'b010011WR_DATA_CS_FIN26'b010010WR_DATA_CHK_RESP6'b010100WR_RESP_TOUT12'hf00WT_REQ6'b000100WRITE_DATA_ERROR2'b10WR_BUSY_INIT_LOOP6'b101101WR_DATA_REQ_RESP_ST6'b010101WR_DATA_REQ_RESP_ST6'b010101WR_DATA_DEL6'b101111WR_DATA_REQ_RESP_FIN6'b010110WR_DATA_CHK_RESP6'b010100WR_DATA_DEL6'b101111WR_DATA_REQ_RESP_FIN6'b010110ST_RW_SD6'b000000SPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZ
# end
# entity
sendCmd
# storage
db|test.(7).cnf
db|test.(7).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RTL|sendCmd.v
60d843724b1c9a299df86ea74dc59972
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# include_file {
RTL|timescale.v
90acbbce5b36e269c098dfecb82797
}
# hierarchies {
spiMaster:inst|sendCmd:u_sendCmd
}
# macro_sequence
WT_CMD5'b10001CMD_SEND_FF_ST5'b01111ST_S_CMD5'b10010WT_CMD5'b10001CMD_D_BYTE2_FIN5'b00000CMD_D_BYTE3_ST5'b01010CMD_D_BYTE2_ST5'b00001CMD_D_BYTE2_FIN5'b00000CMD_SEND_FF_FIN5'b00010CMD_CMD_BYTE_ST5'b10000CMD_CMD_BYTE_FIN5'b00011CMD_D_BYTE1_ST5'b01000CMD_D_BYTE1_FIN5'b00100CMD_D_BYTE2_ST5'b00001CMD_REQ_RESP_ST5'b00101CMD_DEL5'b10011CMD_REQ_RESP_FIN5'b00110CMD_CHK_RESP5'b00111CMD_CHK_RESP5'b00111WT_CMD5'b10001WT_CMD5'b10001CMD_REQ_RESP_ST5'b00101CMD_D_BYTE1_ST5'b01000CMD_D_BYTE1_FIN5'b00100CMD_D_BYTE3_FIN5'b01001CMD_D_BYTE4_ST5'b01100CMD_D_BYTE3_ST5'b01010CMD_D_BYTE3_FIN5'b01001CMD_D_BYTE4_FIN5'b01011CMD_CS_ST5'b01110CMD_D_BYTE4_ST5'b01100CMD_D_BYTE4_FIN5'b01011CMD_CS_FIN5'b01101CMD_REQ_RESP_ST5'b00101CMD_CS_ST5'b01110CMD_CS_FIN5'b01101CMD_SEND_FF_ST5'b01111CMD_SEND_FF_FIN5'b00010CMD_CMD_BYTE_ST5'b10000CMD_CMD_BYTE_FIN5'b00011CMD_DEL5'b10011CMD_REQ_RESP_FIN5'b00110ST_S_CMD5'b10010SPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZ
# end
# entity
spiTxRxData
# storage
db|test.(8).cnf
db|test.(8).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RTL|spiTxRxData.v
5ac4a27e239c4f08a293c6951b7fe37
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
spiMaster:inst|spiTxRxData:u_spiTxRxData
}
# macro_sequence
SPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZ
# end
# entity
readWriteSPIWireData
# storage
db|test.(9).cnf
db|test.(9).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RTL|readWriteSPIWireData.v
458dcc76254a4f316c8b9f34542a44e
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# include_file {
RTL|timescale.v
90acbbce5b36e269c098dfecb82797
RTL|spiMaster_defines.v
f1748e4cb2521cee5037f75263ccf249
}
# hierarchies {
spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData
}
# macro_sequence
WT_TX_DATA2'b00CLK_HI2'b01CLK_HI2'b01CLK_LO2'b10CLK_LO2'b10CLK_HI2'b01WT_TX_DATA2'b00CLK_HI2'b01ST_RW_WIRE2'b11WT_TX_DATA2'b00ST_RW_WIRE2'b11SPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZ
# end
# entity
sm_TxFifo
# storage
db|test.(10).cnf
db|test.(10).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RTL|sm_TxFifo.v
8b95b2675d3428c7f41533ae55ba1ba
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
FIFO_DEPTH
512
PARAMETER_SIGNED_DEC
USR
ADDR_WIDTH
9
PARAMETER_SIGNED_DEC
USR
}
# include_file {
RTL|timescale.v
90acbbce5b36e269c098dfecb82797
}
# hierarchies {
spiMaster:inst|sm_TxFifo:u_sm_txFifo
}
# macro_sequence
SPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZ
# end
# entity
sm_fifoRTL
# storage
db|test.(11).cnf
db|test.(11).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RTL|sm_fifoRTL.v
19dcc4a75c5cfa3a8559e8e7a6d96e82
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
FIFO_WIDTH
8
PARAMETER_SIGNED_DEC
USR
FIFO_DEPTH
512
PARAMETER_SIGNED_DEC
USR
ADDR_WIDTH
9
PARAMETER_SIGNED_DEC
USR
}
# include_file {
RTL|timescale.v
90acbbce5b36e269c098dfecb82797
}
# hierarchies {
spiMaster:inst|sm_TxFifo:u_sm_txFifo|sm_fifoRTL:u_sm_fifo
spiMaster:inst|sm_RxFifo:u_sm_rxFifo|sm_fifoRTL:u_sm_fifo
}
# macro_sequence
SPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZ
# end
# entity
sm_dpMem_dc
# storage
db|test.(12).cnf
db|test.(12).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RTL|sm_dpMem_dc.v
2b78c46cc7e7258130342714c55269
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
FIFO_WIDTH
8
PARAMETER_SIGNED_DEC
USR
FIFO_DEPTH
512
PARAMETER_SIGNED_DEC
USR
ADDR_WIDTH
9
PARAMETER_SIGNED_DEC
USR
}
# include_file {
RTL|timescale.v
90acbbce5b36e269c098dfecb82797
}
# hierarchies {
spiMaster:inst|sm_TxFifo:u_sm_txFifo|sm_fifoRTL:u_sm_fifo|sm_dpMem_dc:u_sm_dpMem_dc
spiMaster:inst|sm_RxFifo:u_sm_rxFifo|sm_fifoRTL:u_sm_fifo|sm_dpMem_dc:u_sm_dpMem_dc
}
# macro_sequence
SPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZ
# end
# entity
sm_TxfifoBI
# storage
db|test.(13).cnf
db|test.(13).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RTL|sm_TxFifoBI.v
4a8bac5f95d7e8c828f8eae4869a7683
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# include_file {
RTL|timescale.v
90acbbce5b36e269c098dfecb82797
RTL|spiMaster_defines.v
f1748e4cb2521cee5037f75263ccf249
}
# hierarchies {
spiMaster:inst|sm_TxFifo:u_sm_txFifo|sm_TxfifoBI:u_sm_TxfifoBI
}
# macro_sequence
FIFO_CONTROL_REG3'b100FIFO_DATA_REG3'b000SPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZ
# end
# entity
sm_RxFifo
# storage
db|test.(14).cnf
db|test.(14).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RTL|sm_RxFifo.v
4f7876f097e65c535588f893ac9af2a
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# user_parameter {
FIFO_DEPTH
512
PARAMETER_SIGNED_DEC
USR
ADDR_WIDTH
9
PARAMETER_SIGNED_DEC
USR
}
# include_file {
RTL|timescale.v
90acbbce5b36e269c098dfecb82797
}
# hierarchies {
spiMaster:inst|sm_RxFifo:u_sm_rxFifo
}
# macro_sequence
SPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZ
# end
# entity
sm_RxfifoBI
# storage
db|test.(15).cnf
db|test.(15).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RTL|sm_RxFifoBI.v
5f8eff1c360dc6d1087c150f72133b1
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# include_file {
RTL|timescale.v
90acbbce5b36e269c098dfecb82797
RTL|spiMaster_defines.v
f1748e4cb2521cee5037f75263ccf249
}
# hierarchies {
spiMaster:inst|sm_RxFifo:u_sm_rxFifo|sm_RxfifoBI:u_sm_RxfifoBI
}
# macro_sequence
FIFO_CONTROL_REG3'b100FIFO_DATA_REG3'b000FIFO_DATA_COUNT_MSB3'b010FIFO_DATA_COUNT_LSB3'b011FIFO_DATA_REG3'b000SPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZSPI_SYS_CLK_48MHZ
# end
# entity
counter
# storage
db|test.(17).cnf
db|test.(17).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
counter.vhd
f9750e3793e37de91ffa96a781450f1
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
counter_end
60000
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
datasource:inst1|counter:U1
}
# lmf
c:|altera|81|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
counter
# storage
db|test.(18).cnf
db|test.(18).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
counter.vhd
f9750e3793e37de91ffa96a781450f1
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
counter_end
56000000
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
datasource:inst1|counter:U2
datasource:inst1|counter:U4
}
# lmf
c:|altera|81|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
counter
# storage
db|test.(19).cnf
db|test.(19).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
counter.vhd
f9750e3793e37de91ffa96a781450f1
5
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
counter_end
100000
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
datasource:inst1|counter:U3
}
# lmf
c:|altera|81|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
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