test.tan.qmsg

实现了对SD卡的SPI方式下读写操作

{ "Info" "ITDB_TSU_RESULT" "spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|rxDataShiftReg\[0\] spidata_in clk_in 7.605 ns register " "Info: tsu for register \"spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|rxDataShiftReg\[0\]\" (data pin = \"spidata_in\", clock pin = \"clk_in\") is 7.605 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.725 ns + Longest pin register " "Info: + Longest pin to register delay is 7.725 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns spidata_in 1 PIN PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_24; Fanout = 1; PIN Node = 'spidata_in'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { spidata_in } "NODE_NAME" } } { "test.bdf" "" { Schematic "E:/spi_Master/test.bdf" { { 328 672 840 344 "spidata_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.306 ns) + CELL(0.366 ns) 7.617 ns spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|Selector20~15 2 COMB LCCOMB_X20_Y6_N0 1 " "Info: 2: + IC(6.306 ns) + CELL(0.366 ns) = 7.617 ns; Loc. = LCCOMB_X20_Y6_N0; Fanout = 1; COMB Node = 'spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|Selector20~15'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.672 ns" { spidata_in spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|Selector20~15 } "NODE_NAME" } } { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.725 ns spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|rxDataShiftReg\[0\] 3 REG LCFF_X20_Y6_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.725 ns; Loc. = LCFF_X20_Y6_N1; Fanout = 2; REG Node = 'spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|rxDataShiftReg\[0\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|Selector20~15 spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|rxDataShiftReg[0] } "NODE_NAME" } } { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 198 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.419 ns ( 18.37 % ) " "Info: Total cell delay = 1.419 ns ( 18.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.306 ns ( 81.63 % ) " "Info: Total interconnect delay = 6.306 ns ( 81.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.725 ns" { spidata_in spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|Selector20~15 spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|rxDataShiftReg[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "7.725 ns" { spidata_in {} spidata_in~combout {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|Selector20~15 {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|rxDataShiftReg[0] {} } { 0.000ns 0.000ns 6.306ns 0.000ns } { 0.000ns 0.945ns 0.366ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 198 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_PLL_OFFSET" "clk_in pll48m:inst2\|altpll:altpll_component\|_clk0 -2.243 ns - " "Info: - Offset between input clock \"clk_in\" and output clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" is -2.243 ns" {  } { { "test.bdf" "" { Schematic "E:/spi_Master/test.bdf" { { 88 -72 96 104 "clk_in" "" } { 8 112 176 24 "clk_in" "" } } } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll48m:inst2\|altpll:altpll_component\|_clk0 destination 2.323 ns - Shortest register " "Info: - Shortest clock path from clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" to destination register is 2.323 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll48m:inst2\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll48m:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.837 ns) + CELL(0.000 ns) 0.837 ns pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 236 " "Info: 2: + IC(0.837 ns) + CELL(0.000 ns) = 0.837 ns; Loc. = CLKCTRL_G3; Fanout = 236; COMB Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.837 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.820 ns) + CELL(0.666 ns) 2.323 ns spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|rxDataShiftReg\[0\] 3 REG LCFF_X20_Y6_N1 2 " "Info: 3: + IC(0.820 ns) + CELL(0.666 ns) = 2.323 ns; Loc. = LCFF_X20_Y6_N1; Fanout = 2; REG Node = 'spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|rxDataShiftReg\[0\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.486 ns" { pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|rxDataShiftReg[0] } "NODE_NAME" } } { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 198 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 28.67 % ) " "Info: Total cell delay = 0.666 ns ( 28.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.657 ns ( 71.33 % ) " "Info: Total interconnect delay = 1.657 ns ( 71.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.323 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|rxDataShiftReg[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.323 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|rxDataShiftReg[0] {} } { 0.000ns 0.837ns 0.820ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.725 ns" { spidata_in spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|Selector20~15 spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|rxDataShiftReg[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "7.725 ns" { spidata_in {} spidata_in~combout {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|Selector20~15 {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|rxDataShiftReg[0] {} } { 0.000ns 0.000ns 6.306ns 0.000ns } { 0.000ns 0.945ns 0.366ns 0.108ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.323 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|rxDataShiftReg[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.323 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|rxDataShiftReg[0] {} } { 0.000ns 0.837ns 0.820ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_in datawrite spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut 6.642 ns register " "Info: tco from clock \"clk_in\" to destination pin \"datawrite\" through register \"spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut\" is 6.642 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "clk_in pll48m:inst2\|altpll:altpll_component\|_clk0 -2.243 ns + " "Info: + Offset between input clock \"clk_in\" and output clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" is -2.243 ns" {  } { { "test.bdf" "" { Schematic "E:/spi_Master/test.bdf" { { 88 -72 96 104 "clk_in" "" } { 8 112 176 24 "clk_in" "" } } } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll48m:inst2\|altpll:altpll_component\|_clk0 source 2.341 ns + Longest register " "Info: + Longest clock path from clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" to source register is 2.341 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll48m:inst2\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll48m:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.837 ns) + CELL(0.000 ns) 0.837 ns pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 236 " "Info: 2: + IC(0.837 ns) + CELL(0.000 ns) = 0.837 ns; Loc. = CLKCTRL_G3; Fanout = 236; COMB Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.837 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.838 ns) + CELL(0.666 ns) 2.341 ns spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut 3 REG LCFF_X20_Y4_N17 2 " "Info: 3: + IC(0.838 ns) + CELL(0.666 ns) = 2.341 ns; Loc. = LCFF_X20_Y4_N17; Fanout = 2; REG Node = 'spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.504 ns" { pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut } "NODE_NAME" } } { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 28.45 % ) " "Info: Total cell delay = 0.666 ns ( 28.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.675 ns ( 71.55 % ) " "Info: Total interconnect delay = 1.675 ns ( 71.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.341 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.341 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut {} } { 0.000ns 0.837ns 0.838ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 60 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.240 ns + Longest register pin " "Info: + Longest register to pin delay is 6.240 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut 1 REG LCFF_X20_Y4_N17 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X20_Y4_N17; Fanout = 2; REG Node = 'spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut } "NODE_NAME" } } { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.184 ns) + CELL(3.056 ns) 6.240 ns datawrite 2 PIN PIN_9 0 " "Info: 2: + IC(3.184 ns) + CELL(3.056 ns) = 6.240 ns; Loc. = PIN_9; Fanout = 0; PIN Node = 'datawrite'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.240 ns" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut datawrite } "NODE_NAME" } } { "test.bdf" "" { Schematic "E:/spi_Master/test.bdf" { { 216 680 856 232 "datawrite" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.056 ns ( 48.97 % ) " "Info: Total cell delay = 3.056 ns ( 48.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.184 ns ( 51.03 % ) " "Info: Total interconnect delay = 3.184 ns ( 51.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.240 ns" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut datawrite } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "6.240 ns" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut {} datawrite {} } { 0.000ns 3.184ns } { 0.000ns 3.056ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.341 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.341 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut {} } { 0.000ns 0.837ns 0.838ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.240 ns" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut datawrite } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "6.240 ns" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut {} datawrite {} } { 0.000ns 3.184ns } { 0.000ns 3.056ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|rxDataShiftReg\[0\] spidata_in clk_in -7.339 ns register " "Info: th for register \"spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|rxDataShiftReg\[0\]\" (data pin = \"spidata_in\", clock pin = \"clk_in\") is -7.339 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "clk_in pll48m:inst2\|altpll:altpll_component\|_clk0 -2.243 ns + " "Info: + Offset between input clock \"clk_in\" and output clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" is -2.243 ns" {  } { { "test.bdf" "" { Schematic "E:/spi_Master/test.bdf" { { 88 -72 96 104 "clk_in" "" } { 8 112 176 24 "clk_in" "" } } } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll48m:inst2\|altpll:altpll_component\|_clk0 destination 2.323 ns + Longest register " "Info: + Longest clock path from clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" to destination register is 2.323 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll48m:inst2\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll48m:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.837 ns) + CELL(0.000 ns) 0.837 ns pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 236 " "Info: 2: + IC(0.837 ns) + CELL(0.000 ns) = 0.837 ns; Loc. = CLKCTRL_G3; Fanout = 236; COMB Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.837 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.820 ns) + CELL(0.666 ns) 2.323 ns spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|rxDataShiftReg\[0\] 3 REG LCFF_X20_Y6_N1 2 " "Info: 3: + IC(0.820 ns) + CELL(0.666 ns) = 2.323 ns; Loc. = LCFF_X20_Y6_N1; Fanout = 2; REG Node = 'spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|rxDataShiftReg\[0\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.486 ns" { pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|rxDataShiftReg[0] } "NODE_NAME" } } { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 198 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 28.67 % ) " "Info: Total cell delay = 0.666 ns ( 28.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.657 ns ( 71.33 % ) " "Info: Total interconnect delay = 1.657 ns ( 71.33 % )" {