test.tan.qmsg

实现了对SD卡的SPI方式下读写操作

{ "Info" "ITDB_FULL_SLACK_RESULT" "pll48m:inst2\|altpll:altpll_component\|_clk0 register spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|timeOutCnt\[8\] register spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|CurrState_rwBlkSt.000100 13.86 ns " "Info: Slack time is 13.86 ns for clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" between source register \"spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|timeOutCnt\[8\]\" and destination register \"spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|CurrState_rwBlkSt.000100\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "144.09 MHz 6.94 ns " "Info: Fmax is 144.09 MHz (period= 6.94 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "20.536 ns + Largest register register " "Info: + Largest register to register requirement is 20.536 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.800 ns + " "Info: + Setup relationship between source and destination is 20.800 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 18.557 ns " "Info: + Latch edge is 18.557 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pll48m:inst2\|altpll:altpll_component\|_clk0 20.800 ns -2.243 ns  50 " "Info: Clock period of Destination clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" is 20.800 ns with  offset of -2.243 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.243 ns " "Info: - Launch edge is -2.243 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pll48m:inst2\|altpll:altpll_component\|_clk0 20.800 ns -2.243 ns  50 " "Info: Clock period of Source clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" is 20.800 ns with  offset of -2.243 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll48m:inst2\|altpll:altpll_component\|_clk0 destination 2.345 ns + Shortest register " "Info: + Shortest clock path from clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" to destination register is 2.345 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll48m:inst2\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll48m:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.837 ns) + CELL(0.000 ns) 0.837 ns pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 236 " "Info: 2: + IC(0.837 ns) + CELL(0.000 ns) = 0.837 ns; Loc. = CLKCTRL_G3; Fanout = 236; COMB Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.837 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.842 ns) + CELL(0.666 ns) 2.345 ns spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|CurrState_rwBlkSt.000100 3 REG LCFF_X24_Y8_N19 6 " "Info: 3: + IC(0.842 ns) + CELL(0.666 ns) = 2.345 ns; Loc. = LCFF_X24_Y8_N19; Fanout = 6; REG Node = 'spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|CurrState_rwBlkSt.000100'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.508 ns" { pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|CurrState_rwBlkSt.000100 } "NODE_NAME" } } { "RTL/readWriteSDBlock.v" "" { Text "E:/spi_Master/RTL/readWriteSDBlock.v" 170 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 28.40 % ) " "Info: Total cell delay = 0.666 ns ( 28.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.679 ns ( 71.60 % ) " "Info: Total interconnect delay = 1.679 ns ( 71.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.345 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|CurrState_rwBlkSt.000100 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.345 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|CurrState_rwBlkSt.000100 {} } { 0.000ns 0.837ns 0.842ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll48m:inst2\|altpll:altpll_component\|_clk0 source 2.345 ns - Longest register " "Info: - Longest clock path from clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" to source register is 2.345 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll48m:inst2\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll48m:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.837 ns) + CELL(0.000 ns) 0.837 ns pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 236 " "Info: 2: + IC(0.837 ns) + CELL(0.000 ns) = 0.837 ns; Loc. = CLKCTRL_G3; Fanout = 236; COMB Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.837 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.842 ns) + CELL(0.666 ns) 2.345 ns spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|timeOutCnt\[8\] 3 REG LCFF_X25_Y8_N23 4 " "Info: 3: + IC(0.842 ns) + CELL(0.666 ns) = 2.345 ns; Loc. = LCFF_X25_Y8_N23; Fanout = 4; REG Node = 'spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|timeOutCnt\[8\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.508 ns" { pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[8] } "NODE_NAME" } } { "RTL/readWriteSDBlock.v" "" { Text "E:/spi_Master/RTL/readWriteSDBlock.v" 676 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 28.40 % ) " "Info: Total cell delay = 0.666 ns ( 28.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.679 ns ( 71.60 % ) " "Info: Total interconnect delay = 1.679 ns ( 71.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.345 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[8] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.345 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[8] {} } { 0.000ns 0.837ns 0.842ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.345 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|CurrState_rwBlkSt.000100 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.345 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|CurrState_rwBlkSt.000100 {} } { 0.000ns 0.837ns 0.842ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.345 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[8] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.345 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[8] {} } { 0.000ns 0.837ns 0.842ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "RTL/readWriteSDBlock.v" "" { Text "E:/spi_Master/RTL/readWriteSDBlock.v" 676 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns - " "Info: - Micro setup delay of destination is -0.040 ns" {  } { { "RTL/readWriteSDBlock.v" "" { Text "E:/spi_Master/RTL/readWriteSDBlock.v" 170 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.345 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|CurrState_rwBlkSt.000100 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.345 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|CurrState_rwBlkSt.000100 {} } { 0.000ns 0.837ns 0.842ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.345 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[8] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.345 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[8] {} } { 0.000ns 0.837ns 0.842ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.676 ns - Longest register register " "Info: - Longest register to register delay is 6.676 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|timeOutCnt\[8\] 1 REG LCFF_X25_Y8_N23 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y8_N23; Fanout = 4; REG Node = 'spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|timeOutCnt\[8\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[8] } "NODE_NAME" } } { "RTL/readWriteSDBlock.v" "" { Text "E:/spi_Master/RTL/readWriteSDBlock.v" 676 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.140 ns) + CELL(0.534 ns) 1.674 ns spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|Equal7~103 2 COMB LCCOMB_X24_Y8_N24 2 " "Info: 2: + IC(1.140 ns) + CELL(0.534 ns) = 1.674 ns; Loc. = LCCOMB_X24_Y8_N24; Fanout = 2; COMB Node = 'spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|Equal7~103'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.674 ns" { spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[8] spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal7~103 } "NODE_NAME" } } { "RTL/readWriteSDBlock.v" "" { Text "E:/spi_Master/RTL/readWriteSDBlock.v" 428 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.048 ns) + CELL(0.614 ns) 3.336 ns spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|Equal7~105 3 COMB LCCOMB_X25_Y8_N0 4 " "Info: 3: + IC(1.048 ns) + CELL(0.614 ns) = 3.336 ns; Loc. = LCCOMB_X25_Y8_N0; Fanout = 4; COMB Node = 'spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|Equal7~105'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.662 ns" { spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal7~103 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal7~105 } "NODE_NAME" } } { "RTL/readWriteSDBlock.v" "" { Text "E:/spi_Master/RTL/readWriteSDBlock.v" 428 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.890 ns) + CELL(0.651 ns) 5.877 ns spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|CurrState_rwBlkSt.000100~50 4 COMB LCCOMB_X24_Y8_N4 1 " "Info: 4: + IC(1.890 ns) + CELL(0.651 ns) = 5.877 ns; Loc. = LCCOMB_X24_Y8_N4; Fanout = 1; COMB Node = 'spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|CurrState_rwBlkSt.000100~50'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.541 ns" { spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal7~105 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|CurrState_rwBlkSt.000100~50 } "NODE_NAME" } } { "RTL/readWriteSDBlock.v" "" { Text "E:/spi_Master/RTL/readWriteSDBlock.v" 170 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.372 ns) + CELL(0.319 ns) 6.568 ns spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|CurrState_rwBlkSt.000100~52 5 COMB LCCOMB_X24_Y8_N18 1 " "Info: 5: + IC(0.372 ns) + CELL(0.319 ns) = 6.568 ns; Loc. = LCCOMB_X24_Y8_N18; Fanout = 1; COMB Node = 'spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|CurrState_rwBlkSt.000100~52'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.691 ns" { spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|CurrState_rwBlkSt.000100~50 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|CurrState_rwBlkSt.000100~52 } "NODE_NAME" } } { "RTL/readWriteSDBlock.v" "" { Text "E:/spi_Master/RTL/readWriteSDBlock.v" 170 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.676 ns spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|CurrState_rwBlkSt.000100 6 REG LCFF_X24_Y8_N19 6 " "Info: 6: + IC(0.000 ns) + CELL(0.108 ns) = 6.676 ns; Loc. = LCFF_X24_Y8_N19; Fanout = 6; REG Node = 'spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|CurrState_rwBlkSt.000100'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|CurrState_rwBlkSt.000100~52 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|CurrState_rwBlkSt.000100 } "NODE_NAME" } } { "RTL/readWriteSDBlock.v" "" { Text "E:/spi_Master/RTL/readWriteSDBlock.v" 170 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.226 ns ( 33.34 % ) " "Info: Total cell delay = 2.226 ns ( 33.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.450 ns ( 66.66 % ) " "Info: Total interconnect delay = 4.450 ns ( 66.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.676 ns" { spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[8] spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal7~103 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal7~105 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|CurrState_rwBlkSt.000100~50 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|CurrState_rwBlkSt.000100~52 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|CurrState_rwBlkSt.000100 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "6.676 ns" { spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[8] {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal7~103 {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal7~105 {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|CurrState_rwBlkSt.000100~50 {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|CurrState_rwBlkSt.000100~52 {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|CurrState_rwBlkSt.000100 {} } { 0.000ns 1.140ns 1.048ns 1.890ns 0.372ns 0.000ns } { 0.000ns 0.534ns 0.614ns 0.651ns 0.319ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.345 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|CurrState_rwBlkSt.000100 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.345 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|CurrState_rwBlkSt.000100 {} } { 0.000ns 0.837ns 0.842ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.345 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[8] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.345 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[8] {} } { 0.000ns 0.837ns 0.842ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.676 ns" { spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[8] spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal7~103 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal7~105 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|CurrState_rwBlkSt.000100~50 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|CurrState_rwBlkSt.000100~52 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|CurrState_rwBlkSt.000100 } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "6.676 ns" { spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[8] {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal7~103 {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal7~105 {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|CurrState_rwBlkSt.000100~50 {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|CurrState_rwBlkSt.000100~52 {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|CurrState_rwBlkSt.000100 {} } { 0.000ns 1.140ns 1.048ns 1.890ns 0.372ns 0.000ns } { 0.000ns 0.534ns 0.614ns 0.651ns 0.319ns 0.108ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk_in " "Info: No valid register-to-register data paths exist for clock \"clk_in\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "pll48m:inst2\|altpll:altpll_component\|_clk0 register spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut register spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut 499 ps " "Info: Minimum slack time is 499 ps for clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" between source register \"spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut\" and destination register \"spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.501 ns + Shortest register register " "Info: + Shortest register to register delay is 0.501 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut 1 REG LCFF_X20_Y4_N17 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X20_Y4_N17; Fanout = 2; REG Node = 'spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut } "NODE_NAME" } } { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.393 ns) 0.393 ns spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|Selector35~237 2 COMB LCCOMB_X20_Y4_N16 1 " "Info: 2: + IC(0.000 ns) + CELL(0.393 ns) = 0.393 ns; Loc. = LCCOMB_X20_Y4_N16; Fanout = 1; COMB Node = 'spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|Selector35~237'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.393 ns" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|Selector35~237 } "NODE_NAME" } } { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.501 ns spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut 3 REG LCFF_X20_Y4_N17 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.501 ns; Loc. = LCFF_X20_Y4_N17; Fanout = 2; REG Node = 'spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|Selector35~237 spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut } "NODE_NAME" } } { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.501 ns ( 100.00 % ) " "Info: Total cell delay = 0.501 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.501 ns" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|Selector35~237 spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "0.501 ns" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|Selector35~237 {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.002 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.002 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -2.243 ns " "Info: + Latch edge is -2.243 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pll48m:inst2\|altpll:altpll_component\|_clk0 20.800 ns -2.243 ns  50 " "Info: Clock period of Destination clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" is 20.800 ns with  offset of -2.243 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.243 ns " "Info: - Launch edge is -2.243 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pll48m:inst2\|altpll:altpll_component\|_clk0 20.800 ns -2.243 ns  50 " "Info: Clock period of Source clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" is 20.800 ns with  offset of -2.243 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll48m:inst2\|altpll:altpll_component\|_clk0 destination 2.341 ns + Longest register " "Info: + Longest clock path from clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" to destination register is 2.341 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll48m:inst2\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll48m:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.837 ns) + CELL(0.000 ns) 0.837 ns pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 236 " "Info: 2: + IC(0.837 ns) + CELL(0.000 ns) = 0.837 ns; Loc. = CLKCTRL_G3; Fanout = 236; COMB Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.837 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.838 ns) + CELL(0.666 ns) 2.341 ns spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut 3 REG LCFF_X20_Y4_N17 2 " "Info: 3: + IC(0.838 ns) + CELL(0.666 ns) = 2.341 ns; Loc. = LCFF_X20_Y4_N17; Fanout = 2; REG Node = 'spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.504 ns" { pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut } "NODE_NAME" } } { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 28.45 % ) " "Info: Total cell delay = 0.666 ns ( 28.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.675 ns ( 71.55 % ) " "Info: Total interconnect delay = 1.675 ns ( 71.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.341 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.341 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut {} } { 0.000ns 0.837ns 0.838ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll48m:inst2\|altpll:altpll_component\|_clk0 source 2.341 ns - Shortest register " "Info: - Shortest clock path from clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" to source register is 2.341 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll48m:inst2\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll48m:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.837 ns) + CELL(0.000 ns) 0.837 ns pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 236 " "Info: 2: + IC(0.837 ns) + CELL(0.000 ns) = 0.837 ns; Loc. = CLKCTRL_G3; Fanout = 236; COMB Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.837 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.838 ns) + CELL(0.666 ns) 2.341 ns spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut 3 REG LCFF_X20_Y4_N17 2 " "Info: 3: + IC(0.838 ns) + CELL(0.666 ns) = 2.341 ns; Loc. = LCFF_X20_Y4_N17; Fanout = 2; REG Node = 'spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.504 ns" { pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut } "NODE_NAME" } } { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 28.45 % ) " "Info: Total cell delay = 0.666 ns ( 28.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.675 ns ( 71.55 % ) " "Info: Total interconnect delay = 1.675 ns ( 71.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.341 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.341 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut {} } { 0.000ns 0.837ns 0.838ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.341 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.341 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut {} } { 0.000ns 0.837ns 0.838ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.341 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut {} } { 0.000ns 0.837ns 0.838ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 60 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 60 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.341 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.341 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut {} } { 0.000ns 0.837ns 0.838ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.341 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut {} } { 0.000ns 0.837ns 0.838ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.501 ns" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|Selector35~237 spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "0.501 ns" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|Selector35~237 {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.108ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.341 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.341 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut {} } { 0.000ns 0.837ns 0.838ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.341 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut {} } { 0.000ns 0.837ns 0.838ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 0}