prev_cmp_test.tan.qmsg

实现了对SD卡的SPI方式下读写操作

{ "Info" "ITDB_TSU_RESULT" "spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|rxDataShiftReg\[0\] spidata_in clk_in 6.373 ns register " "Info: tsu for register \"spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|rxDataShiftReg\[0\]\" (data pin = \"spidata_in\", clock pin = \"clk_in\") is 6.373 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.516 ns + Longest pin register " "Info: + Longest pin to register delay is 6.516 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns spidata_in 1 PIN PIN_92 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_92; Fanout = 1; PIN Node = 'spidata_in'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { spidata_in } "NODE_NAME" } } { "test.bdf" "" { Schematic "E:/spi_Master/test.bdf" { { 328 672 840 344 "spidata_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.257 ns) + CELL(0.206 ns) 6.408 ns spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|Selector20~15 2 COMB LCCOMB_X27_Y8_N8 1 " "Info: 2: + IC(5.257 ns) + CELL(0.206 ns) = 6.408 ns; Loc. = LCCOMB_X27_Y8_N8; Fanout = 1; COMB Node = 'spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|Selector20~15'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.463 ns" { spidata_in spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|Selector20~15 } "NODE_NAME" } } { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.516 ns spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|rxDataShiftReg\[0\] 3 REG LCFF_X27_Y8_N9 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 6.516 ns; Loc. = LCFF_X27_Y8_N9; Fanout = 2; REG Node = 'spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|rxDataShiftReg\[0\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|Selector20~15 spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|rxDataShiftReg[0] } "NODE_NAME" } } { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 198 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.259 ns ( 19.32 % ) " "Info: Total cell delay = 1.259 ns ( 19.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.257 ns ( 80.68 % ) " "Info: Total interconnect delay = 5.257 ns ( 80.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.516 ns" { spidata_in spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|Selector20~15 spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|rxDataShiftReg[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "6.516 ns" { spidata_in {} spidata_in~combout {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|Selector20~15 {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|rxDataShiftReg[0] {} } { 0.000ns 0.000ns 5.257ns 0.000ns } { 0.000ns 0.945ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 198 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_PLL_OFFSET" "clk_in pll48m:inst2\|altpll:altpll_component\|_clk0 -2.243 ns - " "Info: - Offset between input clock \"clk_in\" and output clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" is -2.243 ns" {  } { { "test.bdf" "" { Schematic "E:/spi_Master/test.bdf" { { 88 -72 96 104 "clk_in" "" } { 8 112 176 24 "clk_in" "" } } } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll48m:inst2\|altpll:altpll_component\|_clk0 destination 2.346 ns - Shortest register " "Info: - Shortest clock path from clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" to destination register is 2.346 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll48m:inst2\|altpll:altpll_component\|_clk0 1 CLK PLL_1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 2; CLK Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll48m:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.837 ns) + CELL(0.000 ns) 0.837 ns pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G2 235 " "Info: 2: + IC(0.837 ns) + CELL(0.000 ns) = 0.837 ns; Loc. = CLKCTRL_G2; Fanout = 235; COMB Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.837 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.843 ns) + CELL(0.666 ns) 2.346 ns spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|rxDataShiftReg\[0\] 3 REG LCFF_X27_Y8_N9 2 " "Info: 3: + IC(0.843 ns) + CELL(0.666 ns) = 2.346 ns; Loc. = LCFF_X27_Y8_N9; Fanout = 2; REG Node = 'spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|rxDataShiftReg\[0\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.509 ns" { pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|rxDataShiftReg[0] } "NODE_NAME" } } { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 198 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 28.39 % ) " "Info: Total cell delay = 0.666 ns ( 28.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.680 ns ( 71.61 % ) " "Info: Total interconnect delay = 1.680 ns ( 71.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.346 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|rxDataShiftReg[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.346 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|rxDataShiftReg[0] {} } { 0.000ns 0.837ns 0.843ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.516 ns" { spidata_in spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|Selector20~15 spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|rxDataShiftReg[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "6.516 ns" { spidata_in {} spidata_in~combout {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|Selector20~15 {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|rxDataShiftReg[0] {} } { 0.000ns 0.000ns 5.257ns 0.000ns } { 0.000ns 0.945ns 0.206ns 0.108ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.346 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|rxDataShiftReg[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.346 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|rxDataShiftReg[0] {} } { 0.000ns 0.837ns 0.843ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_in spiclk spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiClkOut 5.029 ns register " "Info: tco from clock \"clk_in\" to destination pin \"spiclk\" through register \"spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiClkOut\" is 5.029 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "clk_in pll48m:inst2\|altpll:altpll_component\|_clk0 -2.243 ns + " "Info: + Offset between input clock \"clk_in\" and output clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" is -2.243 ns" {  } { { "test.bdf" "" { Schematic "E:/spi_Master/test.bdf" { { 88 -72 96 104 "clk_in" "" } { 8 112 176 24 "clk_in" "" } } } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll48m:inst2\|altpll:altpll_component\|_clk0 source 2.331 ns + Longest register " "Info: + Longest clock path from clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" to source register is 2.331 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll48m:inst2\|altpll:altpll_component\|_clk0 1 CLK PLL_1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 2; CLK Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll48m:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.837 ns) + CELL(0.000 ns) 0.837 ns pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G2 235 " "Info: 2: + IC(0.837 ns) + CELL(0.000 ns) = 0.837 ns; Loc. = CLKCTRL_G2; Fanout = 235; COMB Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.837 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.828 ns) + CELL(0.666 ns) 2.331 ns spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiClkOut 3 REG LCFF_X25_Y7_N7 2 " "Info: 3: + IC(0.828 ns) + CELL(0.666 ns) = 2.331 ns; Loc. = LCFF_X25_Y7_N7; Fanout = 2; REG Node = 'spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiClkOut'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.494 ns" { pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiClkOut } "NODE_NAME" } } { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 28.57 % ) " "Info: Total cell delay = 0.666 ns ( 28.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.665 ns ( 71.43 % ) " "Info: Total interconnect delay = 1.665 ns ( 71.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.331 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiClkOut } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.331 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiClkOut {} } { 0.000ns 0.837ns 0.828ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 59 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.637 ns + Longest register pin " "Info: + Longest register to pin delay is 4.637 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiClkOut 1 REG LCFF_X25_Y7_N7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y7_N7; Fanout = 2; REG Node = 'spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiClkOut'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiClkOut } "NODE_NAME" } } { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.401 ns) + CELL(3.236 ns) 4.637 ns spiclk 2 PIN PIN_115 0 " "Info: 2: + IC(1.401 ns) + CELL(3.236 ns) = 4.637 ns; Loc. = PIN_115; Fanout = 0; PIN Node = 'spiclk'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.637 ns" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiClkOut spiclk } "NODE_NAME" } } { "test.bdf" "" { Schematic "E:/spi_Master/test.bdf" { { 200 680 856 216 "spiclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.236 ns ( 69.79 % ) " "Info: Total cell delay = 3.236 ns ( 69.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.401 ns ( 30.21 % ) " "Info: Total interconnect delay = 1.401 ns ( 30.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.637 ns" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiClkOut spiclk } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "4.637 ns" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiClkOut {} spiclk {} } { 0.000ns 1.401ns } { 0.000ns 3.236ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.331 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiClkOut } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.331 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiClkOut {} } { 0.000ns 0.837ns 0.828ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.637 ns" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiClkOut spiclk } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "4.637 ns" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiClkOut {} spiclk {} } { 0.000ns 1.401ns } { 0.000ns 3.236ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|rxDataShiftReg\[0\] spidata_in clk_in -6.107 ns register " "Info: th for register \"spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|rxDataShiftReg\[0\]\" (data pin = \"spidata_in\", clock pin = \"clk_in\") is -6.107 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "clk_in pll48m:inst2\|altpll:altpll_component\|_clk0 -2.243 ns + " "Info: + Offset between input clock \"clk_in\" and output clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" is -2.243 ns" {  } { { "test.bdf" "" { Schematic "E:/spi_Master/test.bdf" { { 88 -72 96 104 "clk_in" "" } { 8 112 176 24 "clk_in" "" } } } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll48m:inst2\|altpll:altpll_component\|_clk0 destination 2.346 ns + Longest register " "Info: + Longest clock path from clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" to destination register is 2.346 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll48m:inst2\|altpll:altpll_component\|_clk0 1 CLK PLL_1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 2; CLK Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll48m:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.837 ns) + CELL(0.000 ns) 0.837 ns pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G2 235 " "Info: 2: + IC(0.837 ns) + CELL(0.000 ns) = 0.837 ns; Loc. = CLKCTRL_G2; Fanout = 235; COMB Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.837 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.843 ns) + CELL(0.666 ns) 2.346 ns spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|rxDataShiftReg\[0\] 3 REG LCFF_X27_Y8_N9 2 " "Info: 3: + IC(0.843 ns) + CELL(0.666 ns) = 2.346 ns; Loc. = LCFF_X27_Y8_N9; Fanout = 2; REG Node = 'spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|rxDataShiftReg\[0\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.509 ns" { pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|rxDataShiftReg[0] } "NODE_NAME" } } { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 198 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 28.39 % ) " "Info: Total cell delay = 0.666 ns ( 28.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.680 ns ( 71.61 % ) " "Info: Total interconnect delay = 1.680 ns ( 71.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.346 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|rxDataShiftReg[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.346 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|rxDataShiftReg[0] {} } { 0.000ns 0.837ns 0.843ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 198 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.516 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.516 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns spidata_in 1 PIN PIN_92 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_92; Fanout = 1; PIN Node = 'spidata_in'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { spida