prev_cmp_test.tan.qmsg

实现了对SD卡的SPI方式下读写操作

{ "Info" "ITDB_FULL_SLACK_RESULT" "pll48m:inst2\|altpll:altpll_component\|_clk0 register spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|timeOutCnt\[1\] register spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|delCnt1\[0\] 13.041 ns " "Info: Slack time is 13.041 ns for clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" between source register \"spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|timeOutCnt\[1\]\" and destination register \"spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|delCnt1\[0\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "128.88 MHz 7.759 ns " "Info: Fmax is 128.88 MHz (period= 7.759 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "20.534 ns + Largest register register " "Info: + Largest register to register requirement is 20.534 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.800 ns + " "Info: + Setup relationship between source and destination is 20.800 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 18.557 ns " "Info: + Latch edge is 18.557 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pll48m:inst2\|altpll:altpll_component\|_clk0 20.800 ns -2.243 ns  50 " "Info: Clock period of Destination clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" is 20.800 ns with  offset of -2.243 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.243 ns " "Info: - Launch edge is -2.243 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pll48m:inst2\|altpll:altpll_component\|_clk0 20.800 ns -2.243 ns  50 " "Info: Clock period of Source clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" is 20.800 ns with  offset of -2.243 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.002 ns + Largest " "Info: + Largest clock skew is -0.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll48m:inst2\|altpll:altpll_component\|_clk0 destination 2.351 ns + Shortest register " "Info: + Shortest clock path from clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" to destination register is 2.351 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll48m:inst2\|altpll:altpll_component\|_clk0 1 CLK PLL_1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 2; CLK Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll48m:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.837 ns) + CELL(0.000 ns) 0.837 ns pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G2 235 " "Info: 2: + IC(0.837 ns) + CELL(0.000 ns) = 0.837 ns; Loc. = CLKCTRL_G2; Fanout = 235; COMB Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.837 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.848 ns) + CELL(0.666 ns) 2.351 ns spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|delCnt1\[0\] 3 REG LCFF_X24_Y9_N15 3 " "Info: 3: + IC(0.848 ns) + CELL(0.666 ns) = 2.351 ns; Loc. = LCFF_X24_Y9_N15; Fanout = 3; REG Node = 'spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|delCnt1\[0\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.514 ns" { pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|delCnt1[0] } "NODE_NAME" } } { "RTL/readWriteSDBlock.v" "" { Text "E:/spi_Master/RTL/readWriteSDBlock.v" 676 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 28.33 % ) " "Info: Total cell delay = 0.666 ns ( 28.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.685 ns ( 71.67 % ) " "Info: Total interconnect delay = 1.685 ns ( 71.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.351 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|delCnt1[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.351 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|delCnt1[0] {} } { 0.000ns 0.837ns 0.848ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll48m:inst2\|altpll:altpll_component\|_clk0 source 2.353 ns - Longest register " "Info: - Longest clock path from clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" to source register is 2.353 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll48m:inst2\|altpll:altpll_component\|_clk0 1 CLK PLL_1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 2; CLK Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll48m:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.837 ns) + CELL(0.000 ns) 0.837 ns pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G2 235 " "Info: 2: + IC(0.837 ns) + CELL(0.000 ns) = 0.837 ns; Loc. = CLKCTRL_G2; Fanout = 235; COMB Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.837 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.850 ns) + CELL(0.666 ns) 2.353 ns spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|timeOutCnt\[1\] 3 REG LCFF_X21_Y10_N9 4 " "Info: 3: + IC(0.850 ns) + CELL(0.666 ns) = 2.353 ns; Loc. = LCFF_X21_Y10_N9; Fanout = 4; REG Node = 'spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|timeOutCnt\[1\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.516 ns" { pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[1] } "NODE_NAME" } } { "RTL/readWriteSDBlock.v" "" { Text "E:/spi_Master/RTL/readWriteSDBlock.v" 676 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 28.30 % ) " "Info: Total cell delay = 0.666 ns ( 28.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.687 ns ( 71.70 % ) " "Info: Total interconnect delay = 1.687 ns ( 71.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.353 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[1] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.353 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[1] {} } { 0.000ns 0.837ns 0.850ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.351 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|delCnt1[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.351 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|delCnt1[0] {} } { 0.000ns 0.837ns 0.848ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.353 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[1] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.353 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[1] {} } { 0.000ns 0.837ns 0.850ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "RTL/readWriteSDBlock.v" "" { Text "E:/spi_Master/RTL/readWriteSDBlock.v" 676 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns - " "Info: - Micro setup delay of destination is -0.040 ns" {  } { { "RTL/readWriteSDBlock.v" "" { Text "E:/spi_Master/RTL/readWriteSDBlock.v" 676 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.351 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|delCnt1[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.351 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|delCnt1[0] {} } { 0.000ns 0.837ns 0.848ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.353 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[1] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.353 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[1] {} } { 0.000ns 0.837ns 0.850ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.493 ns - Longest register register " "Info: - Longest register to register delay is 7.493 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|timeOutCnt\[1\] 1 REG LCFF_X21_Y10_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y10_N9; Fanout = 4; REG Node = 'spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|timeOutCnt\[1\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[1] } "NODE_NAME" } } { "RTL/readWriteSDBlock.v" "" { Text "E:/spi_Master/RTL/readWriteSDBlock.v" 676 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.132 ns) + CELL(0.529 ns) 1.661 ns spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|Equal7~101 2 COMB LCCOMB_X22_Y10_N6 2 " "Info: 2: + IC(1.132 ns) + CELL(0.529 ns) = 1.661 ns; Loc. = LCCOMB_X22_Y10_N6; Fanout = 2; COMB Node = 'spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|Equal7~101'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.661 ns" { spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[1] spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal7~101 } "NODE_NAME" } } { "RTL/readWriteSDBlock.v" "" { Text "E:/spi_Master/RTL/readWriteSDBlock.v" 428 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.695 ns) + CELL(0.614 ns) 2.970 ns spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|Equal7~105 3 COMB LCCOMB_X21_Y10_N0 4 " "Info: 3: + IC(0.695 ns) + CELL(0.614 ns) = 2.970 ns; Loc. = LCCOMB_X21_Y10_N0; Fanout = 4; COMB Node = 'spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|Equal7~105'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.309 ns" { spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal7~101 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal7~105 } "NODE_NAME" } } { "RTL/readWriteSDBlock.v" "" { Text "E:/spi_Master/RTL/readWriteSDBlock.v" 428 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.374 ns) + CELL(0.624 ns) 3.968 ns spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|timeOutCnt\[5\]~342 4 COMB LCCOMB_X21_Y10_N4 2 " "Info: 4: + IC(0.374 ns) + CELL(0.624 ns) = 3.968 ns; Loc. = LCCOMB_X21_Y10_N4; Fanout = 2; COMB Node = 'spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|timeOutCnt\[5\]~342'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.998 ns" { spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal7~105 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[5]~342 } "NODE_NAME" } } { "RTL/readWriteSDBlock.v" "" { Text "E:/spi_Master/RTL/readWriteSDBlock.v" 676 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.499 ns) + CELL(0.537 ns) 6.004 ns spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|delCnt1\[5\]~238 5 COMB LCCOMB_X24_Y9_N12 8 " "Info: 5: + IC(1.499 ns) + CELL(0.537 ns) = 6.004 ns; Loc. = LCCOMB_X24_Y9_N12; Fanout = 8; COMB Node = 'spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|delCnt1\[5\]~238'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.036 ns" { spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[5]~342 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|delCnt1[5]~238 } "NODE_NAME" } } { "RTL/readWriteSDBlock.v" "" { Text "E:/spi_Master/RTL/readWriteSDBlock.v" 676 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.634 ns) + CELL(0.855 ns) 7.493 ns spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|delCnt1\[0\] 6 REG LCFF_X24_Y9_N15 3 " "Info: 6: + IC(0.634 ns) + CELL(0.855 ns) = 7.493 ns; Loc. = LCFF_X24_Y9_N15; Fanout = 3; REG Node = 'spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|delCnt1\[0\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.489 ns" { spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|delCnt1[5]~238 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|delCnt1[0] } "NODE_NAME" } } { "RTL/readWriteSDBlock.v" "" { Text "E:/spi_Master/RTL/readWriteSDBlock.v" 676 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.159 ns ( 42.16 % ) " "Info: Total cell delay = 3.159 ns ( 42.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.334 ns ( 57.84 % ) " "Info: Total interconnect delay = 4.334 ns ( 57.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.493 ns" { spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[1] spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal7~101 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal7~105 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[5]~342 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|delCnt1[5]~238 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|delCnt1[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "7.493 ns" { spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[1] {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal7~101 {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal7~105 {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[5]~342 {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|delCnt1[5]~238 {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|delCnt1[0] {} } { 0.000ns 1.132ns 0.695ns 0.374ns 1.499ns 0.634ns } { 0.000ns 0.529ns 0.614ns 0.624ns 0.537ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.351 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|delCnt1[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.351 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|delCnt1[0] {} } { 0.000ns 0.837ns 0.848ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.353 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[1] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.353 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[1] {} } { 0.000ns 0.837ns 0.850ns } { 0.000ns 0.000ns 0.666ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.493 ns" { spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[1] spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal7~101 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal7~105 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[5]~342 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|delCnt1[5]~238 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|delCnt1[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "7.493 ns" { spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[1] {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal7~101 {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal7~105 {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[5]~342 {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|delCnt1[5]~238 {} spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|delCnt1[0] {} } { 0.000ns 1.132ns 0.695ns 0.374ns 1.499ns 0.634ns } { 0.000ns 0.529ns 0.614ns 0.624ns 0.537ns 0.855ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk_in " "Info: No valid register-to-register data paths exist for clock \"clk_in\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "pll48m:inst2\|altpll:altpll_component\|_clk0 register spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut register spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut 499 ps " "Info: Minimum slack time is 499 ps for clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" between source register \"spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut\" and destination register \"spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.501 ns + Shortest register register " "Info: + Shortest register to register delay is 0.501 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut 1 REG LCFF_X25_Y7_N17 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y7_N17; Fanout = 2; REG Node = 'spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut } "NODE_NAME" } } { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.393 ns) 0.393 ns spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|Selector35~237 2 COMB LCCOMB_X25_Y7_N16 1 " "Info: 2: + IC(0.000 ns) + CELL(0.393 ns) = 0.393 ns; Loc. = LCCOMB_X25_Y7_N16; Fanout = 1; COMB Node = 'spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|Selector35~237'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.393 ns" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|Selector35~237 } "NODE_NAME" } } { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 113 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.501 ns spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut 3 REG LCFF_X25_Y7_N17 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.501 ns; Loc. = LCFF_X25_Y7_N17; Fanout = 2; REG Node = 'spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|Selector35~237 spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut } "NODE_NAME" } } { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.501 ns ( 100.00 % ) " "Info: Total cell delay = 0.501 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.501 ns" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|Selector35~237 spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "0.501 ns" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|Selector35~237 {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.002 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.002 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -2.243 ns " "Info: + Latch edge is -2.243 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pll48m:inst2\|altpll:altpll_component\|_clk0 20.800 ns -2.243 ns  50 " "Info: Clock period of Destination clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" is 20.800 ns with  offset of -2.243 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.243 ns " "Info: - Launch edge is -2.243 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pll48m:inst2\|altpll:altpll_component\|_clk0 20.800 ns -2.243 ns  50 " "Info: Clock period of Source clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" is 20.800 ns with  offset of -2.243 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll48m:inst2\|altpll:altpll_component\|_clk0 destination 2.331 ns + Longest register " "Info: + Longest clock path from clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" to destination register is 2.331 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll48m:inst2\|altpll:altpll_component\|_clk0 1 CLK PLL_1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 2; CLK Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll48m:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.837 ns) + CELL(0.000 ns) 0.837 ns pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G2 235 " "Info: 2: + IC(0.837 ns) + CELL(0.000 ns) = 0.837 ns; Loc. = CLKCTRL_G2; Fanout = 235; COMB Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.837 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.828 ns) + CELL(0.666 ns) 2.331 ns spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut 3 REG LCFF_X25_Y7_N17 2 " "Info: 3: + IC(0.828 ns) + CELL(0.666 ns) = 2.331 ns; Loc. = LCFF_X25_Y7_N17; Fanout = 2; REG Node = 'spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.494 ns" { pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut } "NODE_NAME" } } { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 28.57 % ) " "Info: Total cell delay = 0.666 ns ( 28.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.665 ns ( 71.43 % ) " "Info: Total interconnect delay = 1.665 ns ( 71.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.331 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.331 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut {} } { 0.000ns 0.837ns 0.828ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll48m:inst2\|altpll:altpll_component\|_clk0 source 2.331 ns - Shortest register " "Info: - Shortest clock path from clock \"pll48m:inst2\|altpll:altpll_component\|_clk0\" to source register is 2.331 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll48m:inst2\|altpll:altpll_component\|_clk0 1 CLK PLL_1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 2; CLK Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll48m:inst2|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.837 ns) + CELL(0.000 ns) 0.837 ns pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G2 235 " "Info: 2: + IC(0.837 ns) + CELL(0.000 ns) = 0.837 ns; Loc. = CLKCTRL_G2; Fanout = 235; COMB Node = 'pll48m:inst2\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.837 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.828 ns) + CELL(0.666 ns) 2.331 ns spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut 3 REG LCFF_X25_Y7_N17 2 " "Info: 3: + IC(0.828 ns) + CELL(0.666 ns) = 2.331 ns; Loc. = LCFF_X25_Y7_N17; Fanout = 2; REG Node = 'spiMaster:inst\|readWriteSPIWireData:u_readWriteSPIWireData\|spiDataOut'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.494 ns" { pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut } "NODE_NAME" } } { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 60 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 28.57 % ) " "Info: Total cell delay = 0.666 ns ( 28.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.665 ns ( 71.43 % ) " "Info: Total interconnect delay = 1.665 ns ( 71.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.331 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.331 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut {} } { 0.000ns 0.837ns 0.828ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.331 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.331 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut {} } { 0.000ns 0.837ns 0.828ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 60 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "RTL/readWriteSPIWireData.v" "" { Text "E:/spi_Master/RTL/readWriteSPIWireData.v" 60 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.331 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.331 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut {} } { 0.000ns 0.837ns 0.828ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.501 ns" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|Selector35~237 spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "0.501 ns" { spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|Selector35~237 {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.108ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.331 ns" { pll48m:inst2|altpll:altpll_component|_clk0 pll48m:inst2|altpll:altpll_component|_clk0~clkctrl spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "2.331 ns" { pll48m:inst2|altpll:altpll_component|_clk0 {} pll48m:inst2|altpll:altpll_component|_clk0~clkctrl {} spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut {} } { 0.000ns 0.837ns 0.828ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 0}