test.fit.qmsg

实现了对SD卡的SPI方式下读写操作

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0 0}  } {  } 0 0 "Finished register packing" 0 0 "" 0 0}
{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "pll48m:inst2\|altpll:altpll_component\|pll clk\[0\] pllout " "Warning: PLL \"pll48m:inst2\|altpll:altpll_component\|pll\" output port clk\[0\] feeds output pin \"pllout\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "altpll.tdf" "" { Text "c:/altera/81/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } { "pll48m.vhd" "" { Text "E:/spi_Master/pll48m.vhd" 139 0 0 } } { "test.bdf" "" { Schematic "E:/spi_Master/test.bdf" { { -24 176 288 72 "inst2" "" } } } } { "test.bdf" "" { Schematic "E:/spi_Master/test.bdf" { { -40 336 512 -24 "pllout" "" } } } }  } 0 0 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0 0}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:04 " "Info: Fitter preparation operations ending: elapsed time is 00:00:04" {  } {  } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.877 ns register register " "Info: Estimated most critical path is register to register delay of 5.877 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|locRespByte\[5\] 1 REG LAB_X25_Y6 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X25_Y6; Fanout = 2; REG Node = 'spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|locRespByte\[5\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|locRespByte[5] } "NODE_NAME" } } { "RTL/readWriteSDBlock.v" "" { Text "E:/spi_Master/RTL/readWriteSDBlock.v" 676 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.511 ns) + CELL(0.370 ns) 0.881 ns spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|Equal6~66 2 COMB LAB_X25_Y6 1 " "Info: 2: + IC(0.511 ns) + CELL(0.370 ns) = 0.881 ns; Loc. = LAB_X25_Y6; Fanout = 1; COMB Node = 'spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|Equal6~66'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.881 ns" { spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|locRespByte[5] spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal6~66 } "NODE_NAME" } } { "RTL/readWriteSDBlock.v" "" { Text "E:/spi_Master/RTL/readWriteSDBlock.v" 422 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.605 ns) + CELL(0.206 ns) 1.692 ns spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|Equal6~67 3 COMB LAB_X25_Y6 3 " "Info: 3: + IC(0.605 ns) + CELL(0.206 ns) = 1.692 ns; Loc. = LAB_X25_Y6; Fanout = 3; COMB Node = 'spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|Equal6~67'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal6~66 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal6~67 } "NODE_NAME" } } { "RTL/readWriteSDBlock.v" "" { Text "E:/spi_Master/RTL/readWriteSDBlock.v" 422 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.166 ns) + CELL(0.370 ns) 3.228 ns spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|timeOutCnt\[5\]~342 4 COMB LAB_X25_Y8 2 " "Info: 4: + IC(1.166 ns) + CELL(0.370 ns) = 3.228 ns; Loc. = LAB_X25_Y8; Fanout = 2; COMB Node = 'spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|timeOutCnt\[5\]~342'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.536 ns" { spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal6~67 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[5]~342 } "NODE_NAME" } } { "RTL/readWriteSDBlock.v" "" { Text "E:/spi_Master/RTL/readWriteSDBlock.v" 676 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.894 ns) + CELL(0.537 ns) 4.659 ns spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|delCnt1\[5\]~238 5 COMB LAB_X26_Y5 8 " "Info: 5: + IC(0.894 ns) + CELL(0.537 ns) = 4.659 ns; Loc. = LAB_X26_Y5; Fanout = 8; COMB Node = 'spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|delCnt1\[5\]~238'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.431 ns" { spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[5]~342 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|delCnt1[5]~238 } "NODE_NAME" } } { "RTL/readWriteSDBlock.v" "" { Text "E:/spi_Master/RTL/readWriteSDBlock.v" 676 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.363 ns) + CELL(0.855 ns) 5.877 ns spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|delCnt1\[2\] 6 REG LAB_X26_Y5 3 " "Info: 6: + IC(0.363 ns) + CELL(0.855 ns) = 5.877 ns; Loc. = LAB_X26_Y5; Fanout = 3; REG Node = 'spiMaster:inst\|readWriteSDBlock:u_readWriteSDBlock\|delCnt1\[2\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.218 ns" { spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|delCnt1[5]~238 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|delCnt1[2] } "NODE_NAME" } } { "RTL/readWriteSDBlock.v" "" { Text "E:/spi_Master/RTL/readWriteSDBlock.v" 676 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.338 ns ( 39.78 % ) " "Info: Total cell delay = 2.338 ns ( 39.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.539 ns ( 60.22 % ) " "Info: Total interconnect delay = 3.539 ns ( 60.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.877 ns" { spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|locRespByte[5] spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal6~66 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|Equal6~67 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[5]~342 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|delCnt1[5]~238 spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|delCnt1[2] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Average interconnect usage is 1% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X14_Y0 X28_Y14 " "Info: Peak interconnect usage is 2% of the available device resources in the region that extends from location X14_Y0 to location X28_Y14" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "3 " "Warning: Found 3 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "spiclk 0 " "Info: Pin \"spiclk\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "datawrite 0 " "Info: Pin \"datawrite\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "pllout 0 " "Info: Pin \"pllout\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/spi_Master/test.fit.smsg " "Info: Generated suppressed messages file E:/spi_Master/test.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "195 " "Info: Peak virtual memory: 195 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 22 21:04:40 2009 " "Info: Processing ended: Wed Apr 22 21:04:40 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Info: Elapsed time: 00:00:28" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Info: Total CPU time (on all processors): 00:00:09" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}