test.tan.rpt

实现了对SD卡的SPI方式下读写操作

; Worst-case tsu                                            ; N/A       ; None                             ; 7.605 ns                         ; spidata_in                                                            ; spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|rxDataShiftReg[0] ; --                                         ; clk_in                                     ; 0            ;
; Worst-case tco                                            ; N/A       ; None                             ; 6.642 ns                         ; spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut ; datawrite                                                                    ; clk_in                                     ; --                                         ; 0            ;
; Worst-case th                                             ; N/A       ; None                             ; -7.339 ns                        ; spidata_in                                                            ; spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|rxDataShiftReg[0] ; --                                         ; clk_in                                     ; 0            ;
; Clock Setup: 'pll48m:inst2|altpll:altpll_component|_clk0' ; 13.860 ns ; 48.08 MHz ( period = 20.800 ns ) ; 144.09 MHz ( period = 6.940 ns ) ; spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|timeOutCnt[8]      ; spiMaster:inst|readWriteSDBlock:u_readWriteSDBlock|CurrState_rwBlkSt.000100  ; pll48m:inst2|altpll:altpll_component|_clk0 ; pll48m:inst2|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'pll48m:inst2|altpll:altpll_component|_clk0'  ; 0.499 ns  ; 48.08 MHz ( period = 20.800 ns ) ; N/A                              ; spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut ; spiMaster:inst|readWriteSPIWireData:u_readWriteSPIWireData|spiDataOut        ; pll48m:inst2|altpll:altpll_component|_clk0 ; pll48m:inst2|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                              ;           ;                                  ;                                  ;                                                                       ;                                                                              ;                                            ;                                            ; 0            ;
+-----------------------------------------------------------+-----------+----------------------------------+----------------------------------+-----------------------------------------------------------------------+------------------------------------------------------------------------------+--------------------------------------------+--------------------------------------------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2C5T144C8        ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                   ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                          ; Near End           ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                             ;
+--------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                            ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;