📄 counter.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
entity counter is
generic(counter_end : integer);
port (
clk : in std_logic;
counter_out : out integer
);
end counter;
architecture behave of counter is
begin
process(clk)
variable counter_temp : integer := 0;
begin
if rising_edge(clk) then
counter_temp := counter_temp+1;
if counter_temp=counter_end then
counter_temp := 0;
counter_out <= counter_end;
END IF;
end if;
end process;
end behave;
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