📄 startup_i0.lst
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140 .include target.inc ; R8C/Tiny僔儕乕僘梡
141 1 ;""FILE COMMENT""**************************************************************
142 1 ; System Name : for eduction (NO TRANSFERRING)
143 1 ; File Name : targetiinc
144 1 ; Contents : SFR definition file(assembly language) for R8C/Tiny series
145 1 ; Model : for OAKS8-LCD Board
146 1 ; CPU : R8C/Tiny series
147 1 ; Assembler : as30(V.5.10.00)
148 1 ; Linker : ln30(V.5.10.01)
149 1 ; Programer : RENESAS Semiconductor Training Center
150 1 ; Note : for OAKS8-R5F21114FP(R8C/11 group,20MHz)
151 1 ;******************************************************************************
152 1 ; COPYRIGHT(C) 2004 RENESAS TECHNOLOGY CORPORATION
153 1 ; AND RENESAS SOLUTIONS CORPORATION ALL RIGHTS RESERVED
154 1 ;******************************************************************************
155 1 ; History : ---
156 1 ;""FILE COMMENT END""**********************************************************
157 1
158 1 ;******************************************************************************
159 1 ; define SFR symbol
160 1 ;******************************************************************************
161 1 ;------------------------------------------------------------------------------
162 1 ; processor mode register 0
163 1 ;------------------------------------------------------------------------------
164 00000004h 1 pm0 .equ 0004h
165 1 ;------------------------------------------------------------------------------
166 1 ; processor mode register 1
167 1 ;------------------------------------------------------------------------------
168 00000005h 1 pm1 .equ 0005h
169 1 ;------------------------------------------------------------------------------
170 1 ; system clock control register 0
171 1 ;------------------------------------------------------------------------------
172 00000006h 1 cm0 .equ 0006h
173 1 ;------------------------------------------------------------------------------
174 1 ; system clock control register 1
175 1 ;------------------------------------------------------------------------------
176 00000007h 1 cm1 .equ 0007h
177 1 ;------------------------------------------------------------------------------
178 1 ; protect register
179 1 ;------------------------------------------------------------------------------
180 0000000Ah 1 prcr .equ 000ah
181 1 ;
182 0,0000000Ah 1 prc0 .btequ 0,prcr ; bit for permitting writing
183 1 ; system clock control register 0, 1
184 1 ; oscillation stop detection register
185 1 ; high speed ring control register 0, 1
186 1,0000000Ah 1 prc1 .btequ 1,prcr ; bit for permitting writing
* R8C/Tiny SERIES ASSEMBLER * SOURCE LIST Fri Oct 15 10:31:09 2004 PAGE 004
SEQ. LOC. OBJ. 0XMSDA ....*....SOURCE STATEMENT....7....*....8....*....9....*....0....*....1....*....2....*....3....*....4
187 1 ; processor mode register 0, 1
188 2,0000000Ah 1 prc2 .btequ 2,prcr ; bit for permitting writing
189 1 ; port P0 direction register
190 1 ;------------------------------------------------------------------------------
191 1 ; oscillation stop detection register
192 1 ;------------------------------------------------------------------------------
193 0000000Ch 1 ocd .equ 000ch
194 1 ;------------------------------------------------------------------------------
195 1 ; port P1 register
196 1 ;------------------------------------------------------------------------------
197 000000E1h 1 p1 .equ 000E1H
198 1
199 6,000000E1h 1 p1_6 .btequ 6,000E1H; bit 6 of port P1
200 7,000000E1h 1 p1_7 .btequ 7,000E1H; bit 7 of port P1
201 1 ;------------------------------------------------------------------------------
202 1 ; port P1 direction register
203 1 ;------------------------------------------------------------------------------
204 000000E3h 1 pd1 .equ 000E3H ; port P1 direction register
205 1
206 1 ;------------------------------------------------------------------------------
207 1 ; port P4 register
208 1 ;------------------------------------------------------------------------------
209 000000E8h 1 p4 .equ 000E8H
210 5,000000E8h 1 p4_5 .btequ 5,000E8H; bit 5 of port P4(SW20 return input)
211 1
212 1 ;------------------------------------------------------------------------------
213 1 ; INT0 interrupt control register
214 1 ;------------------------------------------------------------------------------
215 0000005Dh 1 int0ic .equ 0005DH
216 3,0000005Dh 1 ir_int0ic .btequ 3,0005DH; INT0 interrupt request bit
217 1
218 1 ;******************************************************************************
219 1 ; end of file
220 1 ;******************************************************************************
221 ; SFR椞堟掕媊僼傽僀儖
222 ;==============================================================================
223 ; 儅僋儘掕媊
224 ;==============================================================================
225 ;-------------------------------------------------------------------------------
226 ; 弶婜抣偺柍偄惷揑曄悢椞堟傪0僋儕傾偡傞張棟偺儅僋儘掕媊
227 ;-------------------------------------------------------------------------------
228 D N_BZERO .macro TOP_ ,SECT_
229 D mov.b #00H, R0L
230 D mov.w #(TOP_ & 0FFFFH), A1
231 D mov.w #sizeof SECT_ , R3
232 D sstr.b
233 .endm
234 ;-------------------------------------------------------------------------------
235 ; 弶婜抣偺偁傞惷揑曄悢椞堟偵弶婜抣傪揮憲偡傞張棟偺儅僋儘掕媊
236 ;-------------------------------------------------------------------------------
237 D N_BCOPY .macro FROM_,TO_,SECT_
238 D mov.w #(FROM_ & 0FFFFH),A0
239 D mov.b #(FROM_ >>16),R1H
240 D mov.w #TO_ ,A1
241 D mov.w #sizeof SECT_ , R3
242 D smovf.b
243 .endm
244 ;==============================================================================
245 ; 僗僞乕僩傾僢僾僾儘僌儔儉椞堟
246 ;==============================================================================
247 .section startup ; 僗僞乕僩傾僢僾僾儘僌儔儉椞堟
248 ;
* R8C/Tiny SERIES ASSEMBLER * SOURCE LIST Fri Oct 15 10:31:09 2004 PAGE 005
SEQ. LOC. OBJ. 0XMSDA ....*....SOURCE STATEMENT....7....*....8....*....9....*....0....*....1....*....2....*....3....*....4
249 .glb start
250 .glb _main
251 .glb _exit
252 .glb $exit
253 00000 start: ; 僗僞乕僩傾僢僾僾儘僌儔儉奐巒傾僪儗僗
254 00000 EB40FF06 ldc #06FFH,ISP ; 妱傝崬傒僗僞僢僋億僀儞僞(ISP)偺弶婜愝掕
255 ; ----- 僾儘僙僢僒儌乕僪儗僕僗僞偺弶婜愝掕 -----
256 00004 7E9F5100 bset prc1 ; 僾儘僙僢僒儌乕僪儗僕僗僞0,1
257 ; 彂偒崬傒僀僱乕僽儖
258 00008 B70400 Z mov.b #00000000B,pm0 ; 僔儞僌儖僠僢僾儌乕僪
259 0000B B70500 Z mov.b #00000000B,pm1 ; 旕奼挘丄僲乕僂僃僀僩
260 0000E 7E8F5100 bclr prc1 ; 僾儘僙僢僒儌乕僪儗僕僗僞0,1
261 ; 彂偒崬傒僨傿僙乕僽儖
262 ; ----- 僔僗僥儉僋儘僢僋惂屼儗僕僗僞偺弶婜愝掕 -----
263 00012 7E9F5000 bset prc0 ; 僔僗僥儉僋儘僢僋惂屼儗僕僗僞0,1
264 ; 彂偒崬傒僀僱乕僽儖
265 00016 C7080600 S mov.b #00001000B,cm0 ; 儊僀儞僋儘僢僋敪怳
266 0001A C7080700 S mov.b #00001000B,cm1 ; 儊僀儞僋儘僢僋暘廃側偟
267 0001E B70C00 Z mov.b #00H,ocd ; 敪怳掆巭専弌儗僕僗僞:儊僀儞僋儘僢僋慖戰
268 00021 7E8F5000 bclr prc0 ; 僔僗僥儉僋儘僢僋惂屼儗僕僗僞0,1
269 ; 彂偒崬傒僨傿僙乕僽儖
270 ;==============================================================================
271
272 00025 EB300000 ldc #0H,FLG ; FLG儗僕僗僞偺弶婜愝掕
273 00029 EB700000 ldc #0H,FB ; FB儗僕僗僞偺弶婜愝掕
274 0002D EB600004 ldc #data_NE_top,SB ; SB儗僕僗僞偺弶婜愝掕
275 ; (for compiler梡)
276 00031 EB200000 ldintb #0FEDCH ; INTB儗僕僗僞弶婜愝掕
EB10DCFE
277 ;
278 00039 F50D00 W jsr RAMCLR ; 僨乕僞椞堟偺0僋儕傾
279 0003C F51F00 W jsr DATINI ; 僨乕僞椞堟傊偺弶婜抣偺揮憲
280 ;
281 0003F EB64 fset I ; 妱崬傒嫋壜(OAKS8-LCDBoard廃曈婡擻儔僀僽儔⌨️ 快捷键说明
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