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<html><body><a href="doc087.html"><img src=../icons/next.gif alt="Next"></a><a href="doc000.html"><img src=../icons/up.gif alt="Up"></a><a href="doc085.html"><img src=../icons/previous.gif alt="Previous"></a><a href="doc000.html"><img src=../icons/contents.gif alt="Contents"></a><a href="doc123.html"><img src=../icons/index.gif alt="Index"></a><hr><h2><a name="sC.3">C.3 Alpha CPUs</a></h2><title>Alpha CPUs</title><p>There are currently 2 generations of CPU core that implement the Alphaarchitecture:<p><ul><li> EV4<li> EV5</ul><p>Opinions differ as to what ``EV'' stands for (Editor's note: the trueanswer is of course ``Electro Vlassic'' See section <a href="doc095.html#sC.12">C.12</a>), but thenumber represents the first generation of Digital's CMOS technologythat the core was implemented in. So, the EV4 was originallyimplemented in CMOS4. As time goes by, a CPU tends to get a mid-lifeperformance kick by being optically shrunk into the next generation ofCMOS process. EV45, then, is the EV4 core implemented in CMOS5process. There is a big difference between shrinking a design into aparticular technology and implementing it from scratch in thattechnology (but I don't want to go into that now). There are a fewother wildcards in here: there is also a CMOS4S (optical shrink inCMOS4) and a CMOS5L. <a name="i252"> <a name="i253"> <a name="i254"><p>True technophiles will be interested to know that CMOS4 is a 0.75 micronprocess, CMOS5 is a 0.5 micron process and CMOS6 is a 0.35 micron process.<p>To map these CPU cores to <em>chips</em> we get:<p><dl><dt><dd>/21064-150,166/ EV4 (originally), EV4S (now)<dt><dd>/21064-200/ EV4S<dt><dd>/21064A-233,275,300/ EV45<dt><dd>/21066/ LCA4S (EV4 core, with EV4 FPU)<dt><dd>/21066A-233/ LCA45 (EV4 core, but with EV45 FPU)<dt><dd>/21164-233,300,333/ EV5<dt><dd>/21164A-417/ EV56<dt><dd>/21264/ You'll just have to wait and see...</dl><p> The EV4 core is a dual-issue (it can issue 2 instructions per CPUclock) superpipelined core with integer unit, floating point unit andbranch prediction. It is fully bypassed and has 64-bit internal datapaths and tightly coupled 8Kbyte caches, one each for Instruction andData. The caches are write-through (they never get dirty).<p><a name="i255"> <a name="i256"> The EV45 core has a couple of tweaks to the EV4 core: it has aslightly improved floating point unit, and 16KB caches, one each forInstruction and Data (it also has cache parity). (Editor's note: NealCrook indicated in a separate mail that the changes to the floatingpoint unit (FPU) improve the performance of the divider. The EV4 FPUdivider takes 34 cycles for a single-precision divide and 63 cyclesfor a double-precision divide (non data-dependent). In constrast, theEV45 divider takes typically 19 cycles (34 cycles max) forsingle-precision and typically 29 cycles (63 cycles max) for adouble-precision division (data-dependent).)<p><a name="i257"> <a name="i258"> The EV5 core is a quad-issue core, also superpipelined, fully bypassedetc etc. It has tightly-coupled 8Kbyte caches, one each for I and D. Thesecaches are write-through. It also has a tightly-coupled 96Kbyte on-chipsecond-level cache (the Scache) which is 3-way set associative and write-back(it can be dirty). The EV4->EV5 performance increase is better than justthe increase achieved by clock speed improvements. As well as the biggercaches and quad issue, there are microarchitectural improvements to reduceproducer/consumer latencies in some paths.<p><a name="i259"> <a name="i260"> The EV56 core is fundamentally the same microarchitecture as theEV5, but it adds some new instructions for 8 and 16-bit loads andstores (see Section <a href="doc091.html#sC.8">C.8</a> Bytes and all that stuff.)These are primarily intended for use by device drivers. TheEV56 core is implemented in CMOS6, which is a 2.0V process.<p> The 21064 was anounced in March 1992. It uses the EV4 core, with a 128-bitbus interface. The bus interface supports the 'easy' connection of an externalsecond-level cache, with a block size of 256-bits (2 data beats on thebus). The Bcache timing is completely software configurable. The 21064 can alsobe configured to use a 64-bit external bus, (but I'm not sure if any shippingsystem uses this mode). The 21064 does not impose any policy on the Bcache, butit is usually configured as a write-back cache. The 21064 does contain hooks toallow external hardware to maintain cache coherence with the Bcache andinternal caches, but this is hairy.<p> The 21066 uses the EV4 core and integrates a memory controller andPCI host bridge. To save pins, the memory controller has a 64-bit databus (but the internal caches have a block size of 256 bits, just likethe 21064, therefore a block fill takes 4 beats on the bus). Thememory controller supports an external Bcache and external DRAMs. Thetiming of the Bcache and DRAMs is completely software configurable,and can be controlled to the resolution of the CPU clockperiod. Having a 4-beat process to fill a cache block isn't as bad asit sounds because the DRAM access is done in page mode. Unfortunately,the memory controller doesn't support any of the new esoteric DRAMs(SDRAM, EDO or BEDO) or synchronous cache RAMs. The PCI bus interfaceis fully rev2.0 compliant and runs at upto 33MHz.<p> The 21164 has a 128-bit data bus and supports split reads, withupto 2 reads outstanding at any time (this allows 100utilisation under best-case dream-on conditions, i.e., you cantheoretically transfer 128-bits of data on every bus clock). The 21164supports easy connection of an external 3-rd level cache (Bcache) andhas all the hooks to allow external systems to maintain full cachecoherence with all caches. Therefore, symmetric multiprocessor designsare 'easy'.<p> The 21164A was announced in October, 1995. It uses the EV56 core. It isnominally pin-compatible with the 21164, but requires split power rails; allof the power pins that were +3.3V power on the 21164 have now been split intotwo groups; one group provided 2.0V power to the CPU core, the other groupsupplies 3.3V to the I/O cells. Unlike older implementations, the 21164 pinsare not 5V-tolerant. The end result of this change is that 21164 systems are,in general, not upgradeable to the 21164A (though note that it would berelatively straightforward to design a 21164A system that could alsoaccommodate a 21164). The 21164A also has a couple of new pins to supportthe new 8 and 16-bit loads and stores. It also improves the 21164 support forusing synchronus SRAMs to implement the external Bcache.<p><p><hr><a href="doc087.html"><img src=../icons/next.gif alt="Next"></a><a href="doc000.html"><img src=../icons/up.gif alt="Up"></a><a href="doc085.html"><img src=../icons/previous.gif alt="Previous"></a><a href="doc000.html"><img src=../icons/contents.gif alt="Contents"></a><a href="doc123.html"><img src=../icons/index.gif alt="Index"></a><hr></body></html>⌨️ 快捷键说明
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