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<html><body><a href="doc092.html"><img src=../icons/next.gif alt="Next"></a><a href="doc000.html"><img src=../icons/up.gif alt="Up"></a><a href="doc090.html"><img src=../icons/previous.gif alt="Previous"></a><a href="doc000.html"><img src=../icons/contents.gif alt="Contents"></a><a href="doc123.html"><img src=../icons/index.gif alt="Index"></a><hr><h2><a name="sC.8">C.8 Bytes and all that stuff</a></h2><title>Bytes and all that stuff</title><p> When the Alpha architecture was introduced, it was unique amongst RISCarchitectures for eschewing 8-bit and 16-bit loads and stores. It supported32-bit and 64-bit loads and stores (longword and quadword, in Digital'snomenclature). The co-architects (Dick Sites, Rich Witek) justified thisdecision by citing the advantages:<p><ol><li> Byte support in the cache and memorysub-system tends to slow down accesses for 32-bit and 64-bit quantities.<li> Byte support makes it hard to build high-speed error-correctioncircuitry into the cache/memory sub-system.</ol><p> Alpha compensates by providing powerful instructions formanipulating bytes and byte groups within 64-bit registers. Standardbenchmarks for string operations (e.g., some of the Byte benchmarks) showthat Alpha performs very well on byte manipulation.<p> The absence of byte loads and stores impacts some software semaphores andimpacts the design of I/O sub-systems. Digital's solution to the I/O problem isto use some low-order address lines to specify the data size during I/Otransfers, and to decode these as byte enables. This so-called SparseAddressing wastes address space and has the consequence that I/O space isnon-contiguous (more on the intricacies of Sparse Addressing when I get aroundto writing it). Note that I/O space, in this context, refers to all systemresources present on the PCI and therefore includes both PCI memory space andPCI I/O space.<p> With the 21164A introduction, the Alpha archtecture was ECO'd to includebyte addressing. Executing these new instructions on an earlier CPU will causean OPCDEC PALcode exception, so that the PALcode will handle the access. Thiswill have a performance impact. The ramifications of this are that use of thesenew instructions (IMO) should be restricted to device drivers rather thanapplications code.<p> These new byte load and stores mean that future support chipsets will beable to support contiguous I/O space.<p><p><hr><a href="doc092.html"><img src=../icons/next.gif alt="Next"></a><a href="doc000.html"><img src=../icons/up.gif alt="Up"></a><a href="doc090.html"><img src=../icons/previous.gif alt="Previous"></a><a href="doc000.html"><img src=../icons/contents.gif alt="Contents"></a><a href="doc123.html"><img src=../icons/index.gif alt="Index"></a><hr></body></html>⌨️ 快捷键说明
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