📄 vovpn-gw.c
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unsigned short val;#endif iop = ioport_addr((immap_t *)CFG_IMMR, 0); /* Reset the PHY */ iop->pdat &= 0xfff7ffff; /* PA12 = |SWITCH_RESET */#if (CONFIG_COMMANDS & CFG_CMD_NET) udelay(20000); iop->pdat |= 0x00080000; for (i=0; i<100; i++) { udelay(20000); if (bb_miiphy_read("FCC1 ETHERNET", CFG_PHY_ADDR,2,&val ) == 0) { break; } } /* initialize switch */ m88e6060_initialize( CFG_PHY_ADDR );#endif}static unsigned long UPMATable[] = { 0x8fffec00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 0 to 3 */ 0x0ffcfc04, 0x3ffdfc00, 0xfffffc01, 0xfffffc01, /* Words 4 to 7 */ 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 8 to 11 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 12 to 15 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 16 to 19 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 20 to 23 */ 0x8fffec00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 24 to 27 */ 0x0ffffc04, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */ 0xfffffc00, 0xfffffc01, 0xfffffc01, 0xfffffc00, /* Words 32 to 35 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 36 to 39 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 40 to 43 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 44 to 47 */ 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 48 to 51 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */ 0xffffec00, 0xffffec04, 0xffffec00, 0xfffffc01 /* Words 60 to 63 */};int board_early_init_f (void){ volatile immap_t *immap; volatile memctl8260_t *memctl; volatile unsigned char *dummy; int i; immap = (immap_t *) CFG_IMMR; memctl = &immap->im_memctl;#if 0 /* CS2-5 - DSP via UPMA */ dummy = (volatile unsigned char *) (memctl->memc_br2 & BRx_BA_MSK); memctl->memc_mar = 0; memctl->memc_mamr = MxMR_OP_WARR; for (i = 0; i < 64; i++) { memctl->memc_mdr = UPMATable[i]; *dummy = 0; } memctl->memc_mamr = 0x00044440;#else /* CS7 - DPRAM via UPMA */ dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK); memctl->memc_mar = 0; memctl->memc_mamr = MxMR_OP_WARR; for (i = 0; i < 64; i++) { memctl->memc_mdr = UPMATable[i]; *dummy = 0; } memctl->memc_mamr = 0x00044440;#endif return 0;}int misc_init_r (void){ volatile ioport_t *iop; unsigned char temp;#if 0 /* DUMP UPMA RAM */ volatile immap_t *immap; volatile memctl8260_t *memctl; volatile unsigned char *dummy; unsigned char c; int i; immap = (immap_t *) CFG_IMMR; memctl = &immap->im_memctl; dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK); memctl->memc_mar = 0; memctl->memc_mamr = MxMR_OP_RARR; for (i = 0; i < 64; i++) { c = *dummy; printf( "UPMA[%02d]: 0x%08lx,0x%08lx: 0x%08lx\n",i, memctl->memc_mamr, memctl->memc_mar, memctl->memc_mdr ); } memctl->memc_mamr = 0x00044440;#endif /* enable buffers (DSP, DPRAM) */ iop = ioport_addr((immap_t *)CFG_IMMR, 0); iop->pdat &= 0xfffbffff; /* PA13 = |EN_M_BCTL1 */ /* destroy DPRAM magic */ *(volatile unsigned char *)0xf0500000 = 0x00; /* clear any pending DPRAM irq */ temp = *(volatile unsigned char *)0xf05003ff; /* write module-id into DPRAM */ *(volatile unsigned char *)0xf0500201 = 0x50; return 0;}#if defined(CONFIG_HAVE_OWN_RESET)intdo_reset (void *cmdtp, int flag, int argc, char *argv[]){ volatile ioport_t *iop; iop = ioport_addr((immap_t *)CFG_IMMR, 2); iop->pdat |= 0x00002000; /* PC18 = HW_RESET */ return 1;}#endif /* CONFIG_HAVE_OWN_RESET */#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)long int initdram (int board_type){#ifndef CFG_RAMBOOT volatile immap_t *immap; volatile memctl8260_t *memctl; volatile uchar *ramaddr; int i; uchar c; immap = (immap_t *) CFG_IMMR; memctl = &immap->im_memctl; ramaddr = (uchar *) CFG_SDRAM_BASE; c = 0xff; immap->im_siu_conf.sc_ppc_acr = 0x02; immap->im_siu_conf.sc_ppc_alrh = 0x01267893; immap->im_siu_conf.sc_ppc_alrl = 0x89abcdef; immap->im_siu_conf.sc_tescr1 = 0x00000000; immap->im_siu_conf.sc_tescr2 = 0x00000000; memctl->memc_mptpr = CFG_MPTPR; memctl->memc_psrt = CFG_PSRT; memctl->memc_or1 = CFG_OR1_PRELIM; memctl->memc_br1 = CFG_SDRAM_BASE | CFG_BR1_PRELIM; /* Precharge all banks */ memctl->memc_psdmr = CFG_PSDMR | 0x28000000; *ramaddr = c; /* CBR refresh */ memctl->memc_psdmr = CFG_PSDMR | 0x08000000; for (i = 0; i < 8; i++) *ramaddr = c; /* Mode Register write */ memctl->memc_psdmr = CFG_PSDMR | 0x18000000; *ramaddr = c; /* Refresh enable */ memctl->memc_psdmr = CFG_PSDMR | 0x40000000; *ramaddr = c;#endif /* CFG_RAMBOOT */ return (CFG_SDRAM_SIZE);}int checkboard (void){#ifdef CONFIG_CLKIN_66MHz puts ("Board: Elmeg VoVPN Gateway Module (66MHz)\n");#else puts ("Board: Elmeg VoVPN Gateway Module (100MHz)\n");#endif return 0;}
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