📄 asm_init.s
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/* * (C) Copyright 2001 ELTEC Elektronik AG * Frank Gottschling <fgottschling@eltec.de> * * ELTEC ELPPC RAM initialization * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */#include <config.h>#include <asm/processor.h>#include <version.h>#include <mpc106.h>#include <ppc_asm.tmpl>#include <ppc_defs.h>.globl board_asm_initboard_asm_init:/* * setup pointer to message block */ mflr r13 /* save away link register */ bl get_lnk_reg /* r3=addr of next instruction */ subi r4, r3, 8 /* r4=board_asm_init addr */ addi r29, r4, (MessageBlock-board_asm_init)/* * dcache_disable */ mfspr r3, HID0 li r4, HID0_DCE andc r3, r3, r4 mr r2, r3 ori r3, r3, HID0_DCI sync mtspr HID0, r3 mtspr HID0, r2 isync sync/* * icache_disable */ mfspr r3, HID0 li r4, 0 ori r4, r4, HID0_ICE andc r3, r3, r4 sync mtspr HID0, r3/* * invalidate caches */ ori r3, r3, (HID0_ICE | HID0_ICFI | HID0_DCI | HID0_DCE) or r4, r4, r3 isync mtspr HID0, r4 andc r4, r4, r3 isync mtspr HID0, r4 isync/* * icache_enable */ mfspr r3, HID0 ori r3, r3, (HID0_ICE | HID0_ICFI) sync mtspr HID0, r3/* * setup memory controller */ lis r1, MPC106_REG_ADDR@h ori r1, r1, MPC106_REG_ADDR@l lis r2, MPC106_REG_DATA@h ori r2, r2, MPC106_REG_DATA@l /* Configure PICR1 */ lis r3, MPC106_REG@h ori r3, r3, PCI_PICR1 stwbrx r3, 0, r1 addis r3, r0, 0xFF14 ori r3, r3, 0x1CC8 eieio stwbrx r3, 0, r2 /* Configure PICR2 */ lis r3, MPC106_REG@h ori r3, r3, PCI_PICR2 stwbrx r3, 0, r1 addis r3, r0, 0x0000 ori r3, r3, 0x0000 eieio stwbrx r3, 0, r2 /* Configure EUMBAR */ lis r3, MPC106_REG@h ori r3, r3, 0x0078 /* offest of EUMBAR in PCI config space */ stwbrx r3, 0, r1 lis r3, MPC107_EUMB_ADDR@h eieio stwbrx r3, 0, r2 /* Configure Address Map B Option Reg */ lis r3, MPC106_REG@h ori r3, r3, 0x00e0 /* offest of AMBOR in PCI config space */ stwbrx r3, 0, r1 lis r3, 0 eieio stwbrx r3, 0, r2 /* Configure I2C Controller */ lis r14, MPC107_I2C_ADDR@h /* base of I2C controller */ ori r14, r14, MPC107_I2C_ADDR@l lis r3, 0x2b10 /* I2C clock = 100MHz/1024 */ stw r3, 4(r14) li r3, 0 /* clear arbitration */ eieio stw r3, 12(r14) /* Configure MCCR1 */ lis r3, MPC106_REG@h ori r3, r3, MPC106_MCCR1 stwbrx r3, 0, r1 addis r3, r0, 0x0660 /* don't set MEMGO now ! */ ori r3, r3, 0x0000 eieio stwbrx r3, 0, r2 /* Configure MCCR2 */ lis r3, MPC106_REG@h ori r3, r3, MPC106_MCCR2 stwbrx r3, 0, r1 addis r3, r0, 0x0400 ori r3, r3, 0x1800 eieio stwbrx r3, 0, r2 /* Configure MCCR3 */ lis r3, MPC106_REG@h ori r3, r3, MPC106_MCCR3 stwbrx r3, 0, r1 addis r3, r0, 0x0230 ori r3, r3, 0x0000 eieio stwbrx r3, 0, r2 /* Configure MCCR4 */ lis r3, MPC106_REG@h ori r3, r3, MPC106_MCCR4 stwbrx r3, 0, r1 addis r3, r0, 0x2532 ori r3, r3, 0x2220 eieio stwbrx r3, 0, r2/* * configure memory interface (MICRs) */ addis r3, r0, 0x8000 /* ADDR_80 */ ori r3, r3, 0x0080 /* SMEMADD1 */ stwbrx r3, 0, r1 addis r3, r0, 0xFFFF ori r3, r3, 0x4000 eieio stwbrx r3, 0, r2 addis r3, r0, 0x8000 /* ADDR_84 */ ori r3, r3, 0x0084 /* SMEMADD2 */ stwbrx r3, 0, r1 addis r3, r0, 0xFFFF ori r3, r3, 0xFFFF eieio stwbrx r3, 0, r2 addis r3, r0, 0x8000 /* ADDR_88 */ ori r3, r3, 0x0088 /* EXTSMEM1 */ stwbrx r3, 0, r1 addis r3, r0, 0x0303 ori r3, r3, 0x0000 eieio stwbrx r3, 0, r2 addis r3, r0, 0x8000 /* ADDR_8C */ ori r3, r3, 0x008c /* EXTSMEM2 */ stwbrx r3, 0, r1 addis r3, r0, 0x0303 ori r3, r3, 0x0303 eieio stwbrx r3, 0, r2 addis r3, r0, 0x8000 /* ADDR_90 */ ori r3, r3, 0x0090 /* EMEMADD1 */ stwbrx r3, 0, r1 addis r3, r0, 0xFFFF ori r3, r3, 0x7F3F eieio stwbrx r3, 0, r2 addis r3, r0, 0x8000 /* ADDR_94 */ ori r3, r3, 0x0094 /* EMEMADD2 */ stwbrx r3, 0, r1 addis r3, r0, 0xFFFF ori r3, r3, 0xFFFF eieio stwbrx r3, 0, r2 addis r3, r0, 0x8000 /* ADDR_98 */ ori r3, r3, 0x0098 /* EXTEMEM1 */ stwbrx r3, 0, r1 addis r3, r0, 0x0303 ori r3, r3, 0x0000 eieio stwbrx r3, 0, r2 addis r3, r0, 0x8000 /* ADDR_9C */ ori r3, r3, 0x009c /* EXTEMEM2 */ stwbrx r3, 0, r1 addis r3, r0, 0x0303 ori r3, r3, 0x0303 eieio stwbrx r3, 0, r2 addis r3, r0, 0x8000 /* ADDR_A0 */ ori r3, r3, 0x00a0 /* MEMBNKEN */ stwbrx r3, 0, r1 addis r3, r0, 0x0000 ori r3, r3, 0x0003 eieio stwbrx r3, 0, r2/* * must wait at least 100us after HRESET to issue a MEMGO */ lis r0, 1 mtctr r0memStartWait: bdnz memStartWait/* * enable RAM Operations through MCCR1 (MEMGO) */ lis r3, 0x8000 ori r3, r3, 0x00f0 stwbrx r3, r0, r1 sync lwbrx r3, 0, r2 lis r0, 0x0008 or r3, r0, r3 stwbrx r3, 0, r2 sync/* * set LEDs first time */ li r3, 0x1 lis r30, CFG_USR_LED_BASE@h stb r3, 2(r30) sync/* * init COM1 for polled output */ lis r8, CFG_NS16550_COM1@h /* COM1 base address*/ ori r8, r8, CFG_NS16550_COM1@l li r9, 0x00 stb r9, 1(r8) /* int disabled */ eieio li r9, 0x00 stb r9, 4(r8) /* modem ctrl */ eieio li r9, 0x80 stb r9, 3(r8) /* link ctrl */ eieio li r9, (CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE) stb r9, 0(r8) /* baud rate (LSB)*/ eieio li r9, ((CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE) >> 8) stb r9, 1(r8) /* baud rate (MSB) */ eieio li r9, 0x07 stb r9, 3(r8) /* 8 data bits, 2 stop bit, no parity */ eieio li r9, 0x0b stb r9, 4(r8) /* enable the receiver and transmitter (modem ctrl) */ eieiowaitEmpty: lbz r9, 5(r8) /* transmit empty */ andi. r9, r9, 0x40 beq waitEmpty li r9, 0x47 stb r9, 3(r8) /* send break, 8 data bits, 2 stop bit, no parity */ eieio lis r0, 0x0001 mtctr r0waitCOM1: lwz r0, 5(r8) /* load from port for delay */ bdnz waitCOM1waitEmpty1: lbz r9, 5(r8) /* transmit empty */ andi. r9, r9, 0x40 beq waitEmpty1 li r9, 0x07 stb r9, 3(r8) /* 8 data bits, 2 stop bit, no parity */ eieio/* * intro message from message block */ addi r3, r29, (MnewLine-MessageBlock) bl Printf addi r3, r29, (MinitLogo-MessageBlock) bl Printf/* * memory cofiguration using SPD information stored on the SODIMMs */ addi r3, r29, (Mspd01-MessageBlock) bl Printf li r17, 0 li r3, 0x0002 /* get RAM type from spd for bank0/1 */ bl spdRead cmpi 0, 0, r3, -1 /* error ? */ bne noSpdError addi r3, r29, (Mfail-MessageBlock) bl Printf li r6, 0xe /* error codes in r6 and r7 */ li r7, 0x0 b toggleError /* fail - loop forever */noSpdError: mr r15, r3 /* save r3 */ addi r3, r29, (Mok-MessageBlock) bl Printf cmpli 0, 0, r15, 0x0004 /* SDRAM ? */ beq isSDRAM addi r3, r29, (MramTyp-MessageBlock) bl Printf li r6, 0xd /* error codes in r6 and r7 */ li r7, 0x0 b toggleError /* fail - loop forever */isSDRAM: li r3, 0x0012 /* get supported CAS latencies from byte 18 */ bl spdRead mr r15, r3 li r3, 0x09 andi. r0, r15, 0x04 bne maxCLis3 li r3, 0x17maxCLis3: andi. r0, r15, 0x02 bne CL2 addi r3, r29, (MramTyp-MessageBlock) bl Printf li r6, 0xc /* error codes in r6 and r7 */ li r7, 0x0 b toggleError /* fail - loop forever */CL2: bl spdRead cmpli 0, 0, r3, 0xa1 /* cycle time must be 10ns max. */ blt speedOk addi r3, r29, (MramTyp-MessageBlock) bl Printf li r6, 0xb /* error codes in r6 and r7 */ li r7, 0x0 b toggleError /* fail - loop forever */speedOk: lis r20, 0x06e8 /* preset MCR1 value */ li r3, 0x0011 /* get number of internal banks from spd for bank0/1 */ bl spdRead cmpli 0, 0, r3, 0x02 beq SD_2B cmpli 0, 0, r3, 0x04 beq SD_4BmemConfErr: addi r3, r29, (MramConfErr-MessageBlock) bl Printf li r6, 0xa /* error codes in r6 and r7 */ li r7, 0x0 b toggleError /* fail - loop forever */SD_2B: li r3, 0x0003 /* get number of row bits from spd for bank0/1 */ bl spdRead cmpli 0, 0, r3, 0x0b beq row11x2 cmpli 0, 0, r3, 0x0c beq row12x2or13x2 cmpli 0, 0, r3, 0x0d beq row12x2or13x2 b memConfErrSD_4B: li r3, 0x0003 /* get number of row bits from spd for bank0/1 */ bl spdRead cmpli 0, 0, r3, 0x0b beq row11x4or12x4 cmpli 0, 0, r3, 0x0c beq row11x4or12x4 cmpli 0, 0, r3, 0x0d beq row13x4 b memConfErrrow12x2or13x2: ori r20, r20, 0x05⌨️ 快捷键说明
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